6th International SoC Conference - Savant Company Inc.

Agenda	Workshops	Registration	Free Exhibit Pass Registration	Testimonials
Abstracts & Bios	Keynote & Panels	Media Registration	Rent an Exhibit Table	Tabletop Exhibit & Reception Information
Presenters' Guidelines	Student Design Contest	Technical Advisory Board	List of Tabletop Exhibits	Hotel Information

6th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

November 5 & 6, 2008 — Radisson Hotel Newport Beach, Southern California

Several Opportunities to Win an iPod shuffle, Technical Books & Many Unique Gifts Throughout the Conference Program . . .
Don't Miss Out!

The Most Informative, Targeted, and Affordably Priced

SoC, ASIC, ASSP, CSSP, FPGA, and Foundry Technology Conference & Exhibit Event of the Year!


	Program Summary
SoC Conference Day 1	Wednesday, November 5, 2008	8:00 am - 6:30 pm
SoC Conference Day 2	Thursday, November 6, 2008	8:00 am - 7:00 pm
SoC Tabletop Exhibit	Wednesday, November 5, 2008	4:30 pm - 8:30 pm
SoC Workshops	Check the Individual Workshop Schedules

Conference Program Agenda*


Day One Wednesday November 5	Session	Company or University
7:00 am – 6:00 pm	Registration Open All Day Several Opportunities to Win an iPod shuffle, Technical Books & Many Unique Gifts Throughout the Conference Program . . . Don't Miss Out!
8:00 - 08:15	Welcome, Opening Remarks, and Conference Updates. Farhad Mafie, President and CEO.	Savant
8:15 – 12:00	New Trends, Technologies, Methodologies, and Products for Your Next Chip Design Track Chairman: Farhad Mafie.
8:15 – 8:45	"SOC - Technology Perspective, Evolution and Challenges." Philip Cacharelis, Engineering Director - Full Service Foundry SBU.	Austria Microsystems AG
8:45 – 9:15	"Advanced Power Management Techniques." Mark Barry, Technology Innovation Manager.	Silicon & Software Systems (S3)
9:15 – 9:45	"Semiconductor SoC, ASIC, FPGA Market update." Jordan Selburn, Silicon Analyst.	iSuppli
9:45 - 10:00	Morning Break
10:00 – 10:30 Keynote	Keynote: "Circuits with Light at the Nanoscale." Dr. Nader Engheta, Professor of Electrical and Systems Engineering, and Professor of, Bioengineering.	University of Pennsylvania
10:30 – 11:00	"FPGAs at the 40nm process node and beyond," Dr. Mojy Chian, Vice President of Technology Development.	Altera
11:00 – 11:30	"A ROI Model for Electronic System Level (ESL) Methodology," Glenn Perry, General Manager, ESL and Design Creation Division.	Mentor Graphics
11:30 – 12:00	"Process Technology Platforms for Analog Intensive Mixed-Signal (AIMS) SoCs," Dr. Samir Chaudhry, Manager - Modeling & Characterization, Jazz Semiconductor.	Jazz Semiconductor
12:00 pm - 1:00 pm	Lunch
1:00 - 2:00 Panel	Panel: “Hardware and Software Challenges for Multicore SoCs in Leading-Edge Applications” Moderator: Robert Cravotta, Technical Editor, Microprocessors, DSPs, Software, and Tools, EDN Worldwide. Panelists: 1: Steve Leibson, Technology Evangelist. 2: Jack Harding, Chairman, President and CEO. 3: Peter Ehlig, P.E., Fellow DSP, Semiconductor Group. 4: Dan Shimizu, AMD Fellow. 5: Glenn Perry, General Manager, ESL and Design Creation Division. 6: Dr. Fadi Maamari, Chief Operating Officer. Opportunity to Win an iPod shuffle During this Panel Discussion . . . Don't Miss Out!	EDN Tensilica eSilicon Texas Instruments AMD Mentor Graphics LogicVision
2:00 – 5:45	Hardware and Software Challenges for Multicore SoCs in Leading-Edge Applications Track Chairman: Farhad Mafie
2:00 – 2:30 Keynote	Keynote: Pranav Mehta, CTO, Embedded & Communications Group.	Intel
2:30 – 3:00	Convenient Concurrency Rules Multicore SOC Design, Steve Leibson, Technology Evangelist.	Tensilica
3:00 – 3:30	Venezia, A New Scalable Multicore Processor for Mobile Multimedia Applications. Hideki Takeda, Senior Specialist, Center for Semiconductor Research & Development Semiconductor Company Toshiba Corporation.	Toshiba
3:30 – 4:00	Design of A VLIW/SMT/Dual-Core SWP-SIMD PLX2 Processor. Professor Sao-Jie Chen.	National Taiwan University
4:00 – 4:15	Afternoon Break
4:15 – 4:45	"General Purpose Processors (GP) vs. Application Specific Processors (ASP), what is the future for multicore designs with 1000's of IPs?" Dr. Nader Bagherzadeh, professor of computer engineering in the department of electrical engineering and computer science, University of California, Irvine.	UCI
4:45 – 5:15	"Boosting System Performance with Multithreaded Multiprocessing." Darren Jones, Engineering Director, Microprocessor Development.	MIPS Technologies
5:15 – 5:45	Is The "True NoC" Just An Urban Engineering Legend? Antonio-Marcello Coppola, Head of the Grenoble Research Laboratory.	ST Microelectronics
4:30 pm - 8:30 pm Exhibit Reception	Conference Exhibit & Reception Open (Free Exhibit Pass)


Day Two Thursday November 6	Session	Company or University
7:00 am – 7:00 pm	Registration Open All Day
8:00 - 8:15	Welcome, Opening Remarks, and Conference Updates. Farhad Mafie, President and CEO.	Savant
8:15 – 12:00	Innovative Embedded Memory Solutions for Complex Multicore SoCs Track Chairman: Dr. Nader Bagherzadeh, University of California, Irvine.
8:15 – 8:45	"NVM Technologies - B4-Flash with its Embedded Application and eCFlash (Logic NVM IP)," Moriyoshi Nakashima, President.	GENUSION
8:45 – 9:15	"Demystifying Logic NVM Options," Charles Ng, VP of Worldwide Sales & Marketing.	Kilopass Technology
9:15 – 9:45	Achieving the Need for Speed in Flash Based Designs. Jim Cooke, Staff Architect and Technologist, NAND Flash.	Micron Technology
9:45 – 10:00	Morning Break
10:00 – 10:30 Keynote	Keynote: "An All Silicon 3D Systems Technology, An Emerging and Disruptive Technology for Convergence of IC, Package and System," Professor Rao R. Tummala, Director of Microsystems Packaging Research Center.	Georgia Institute of Technology
10:30 – 11:00	"Z-RAM: A Better DRAM," Jeff Mitchell, Director of Technical Marketing.	Innovative Silicon
11:00 – 11:30	"Using Data Traffic Efficiency Metrics to Select the Best DDR Memory Controller for your Design," Luigi Ternullo, Product Marketing Manager, STAR Memory System.	Virage Logic
11:30 – 12:00	Innovative 1T Embedded Memories, Esin Terzioglu, Ph.D., Chief Technology Officer and Co-Founder.	Novelics
12:00 – 1:00	Lunch
1:00 – 2:00 Panel	Panel: “Innovative Embedded Memory Solutions for Complex Multicore SoCs” Moderator: John E. Blyler, Editorial Director Chip Design, Embedded Intel, Green Embedded and EE Catalog magazines. Panelists 1: Dr. Mitsumasa Koyanagi, Distinguished Professor, Graduate School of Engineering, Dept., of Bioengineering and Robotics Advanced Bio-Nano Devices Lab. 2: Dr. Dick Foss, Founder and former Chairman of MOSAID. 3: Dr. Virgile Javerliac, MRAM Memory design and Technology Interface for Crocus Technology. 4: Dr. Cyrus Afghahi, CEO, Novelics. 5: Dr. Robert C. Aitken, Fellow, R&D. 6: Alan Aronoff, Vice President of Business Development. Opportunity to Win an iPod shuffle During this Panel Discussion . . . Don't Miss Out!	Chip Design Tohoku University MOSAID Crocus Technology Novelics ARM KeyASIC
2:00 – 5:45	Innovative EDA Tools for Complex SoC Designs in 45nm and beyond. Track Chairman: Professor Rao R. Tummala, Director of Microsystems Packaging Research Center. Georgia Institute of Technology.
2:00 – 2:30 Keynote	Keynote: Automating SoC Design - Reality, Future, or Fiction? Joachim Kunkel, VP and General Manager, Solutions Group.	Synopsys
2:30 – 3:00	"Leveraging ESL Technologies for Low-Power Design," Jon McDonald - Senior Technical Marketing Engineer, ESL and Design Creation Division.	Mentor Graphics
3:00 – 3:30	"ESD Design Challenges in nano-CMOS SoC Design," Benjamin Van Camp, Director of Engineering.	Sarnoff Europe
3:30 – 4:00	"ESL Modeling and Simulation for SoC Architecture and Performance Estimation," Vincent Perrier, co-founder and director.	CoFluent Design
4:00 – 4:15	Afternoon Break
4:15 – 4:45	"Architectural Analysis and Firmware Development for SoC Designs," Bill Neifert, Chief Technical Officer - Founder, VP Business Development.	Carbon Design Systems
4:45 – 5:15	"CyberWorkBench: Integrated Design Environment Based on C based Behavior Synthesis and Verification," Dr. Kazutoshi Wakabayashi.	NEC
5:15 – 5:45	"Scaling Verification with the Open Verification Methodology (OVM)," Thomas L. Anderson, Product Marketing Director.	Cadence Design Systems
5:45 – 6:45 Panel This Panel is FREE for Everyone to Attend!	Panel: “Technology & Entrepreneurship: Dreams, Realities & Opportunities” Moderator: Dr. Goran Matijasevic is Director of Research Development at The Henry Samueli School of Engineering at UC Irvine. Panelists 1: Christopher Harrington, Vice President Strategy & Business Development, Chief CSR Officer, Toshiba America Information Systems. 2: Charles Baecker, Administrative Director, The Don Beall Center for Innovation & Entrepreneurship, The Paul Merage School of Business, UCI. 3: Mark Nielsen, Managing Director of Capistrano Ventures. 4: R. Scott Feldmann, Partner. IP Attorney (hardware & Software). 5: R Sampath, Chair, Quanta Consulting, Inc. IEEE OC Section Chairman. Several Opportunities to Win an iPod shuffle During this Panel Discussion . . . Don't Miss Out!	UC Irvine Toshiba Capistrano Ventures Quanta Consulting IEEE OC Chapter Crowell & Moring Savant

6:45 – 7:00	6th International SoC Conference Closing Remarks. Farhad Mafie, President & CEO.	Savant

* Program is subject to change. Savant Company Inc. reserves the right to revise or modify the above program at its sole discretion.

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