The 16th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

 October 17 & 18, 2018

University of California, Irvine (UCI) - Calit2


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Call for Speakers & Sponsors!

Please submit your proposed Abstract for Technical Advisory Board Review to:


The Theme for This Year’s Conference Is “Silicon Engineering an Automated World."

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Platinum Sponsors


Gold Sponsors





Call for Sponsors and Speakers


The SoC Conference Technical Advisory Board and Organizing Committee are seeking submissions on all aspects of IC & IP Design and Development, Semiconductor Technology, AI Chips, Machine Learning solutions, Mixed-Signal design, FPGA Solutions, eFPGA, ASSP, ASIC, Analog Design Techniques, High-Speed Interfaces and Challenges, CPU/DSP/MCU Cores, RISC-V, GPUs, NPUs, Leading-Edge IPs, Network-on-Chip (NoC), Leading 4 nm Foundries and Designs, Sub 10 nm Design Challenges, SOI Possibilities, Understanding FinFETs, IP Design and Development, IP Reusability, Design for Testing (DFT), Design for Manufacturing (DFM), Chip Design and Verification, 3D-Packaging, Low-Power Design Techniques, EDA Tools and Solutions for complex SoC Platforms, EDA Tools for Analog and Mixed-Signal Designs, New Design Methodologies and Approaches, Technology and Business Challenges, and much more.


Important Information & Date

1. Please submit your proposed abstract for a 25-min technical PowerPoint presentation (1-2 short paragraphs in MS Word –no paper is required) along with the presenter’s picture and bio to the SoC Conference Technical Advisory Board (TAB) and SoC Conference Organizing Committee for review and consideration to by Tuesday, May 1, 2018.

2. If you like to propose an idea for a Panel Discussion, please send us your suggestion (1-2 short paragraphs in MS Word) describing the panel topic, intended audience, and include a list of suggested participants. Please submit your Panel suggestion to by Tuesday, May 1, 2018.  

3. If your organization would like to arrange a ˝ day or a full day Workshop at this targeted conference, please send us your workshop suggestion (1-2 short paragraphs in MSWord) describing topic, length of the workshop, and intended audience. Please submit your Workshop suggestion to: by Wednesday, March 14, 2018.

4. IEEE-OC SSCS Student Design Contest Submissions (sponsored by IEEE SSCS-OC chapter), the contest promotes excellence in the engineering- and computer science-related designs within an academic environment and provides a forum in which undergraduate/graduate engineering and computer science students’ ingenuity can be shared with an audience of academic/industrial technical experts. The participating students will present their designs through posters at the 16th International SoC Conference. Students must submit their project abstracts by
Friday, October 5, 2018, to:

For more information or questions, please contact SoC Organizing Committee: - 949-981-1837

Friday, October 5, 2018: All presentations are due.

“As the industry continues its relentless drive to smaller and smaller geometries, deep technology understanding and strategic business engagements are required to deliver the innovative and complex System-on-Chip (SoC) solutions to a demanding market,” said Professor Michael Green, Chairman of Department of Electrical Engineering and Computer Science, University of California, Irvine. “The annual International System-on-Chip (SoC) Conferences have been an outstanding forum to gather the leading-edge technologies and products from industry leaders and highly-recognized academia into a two-day SoC Conference for those who are involved in designing complex ICs and IPs, researchers, semiconductor and EDA technologists, analysts, and students across the world.”



Topics of Interest


The International System-on-Chip (SoC) Conference, the premier event devoted to Chip Design and Development. . .


The SoC Conference Organizing Committee & Technical Advisory Board are seeking submissions on all aspects of Chip Design & Development including:



  • Semiconductor Technology

  • AI Chips

  • Machine Learning solutions

  • Neural interfaces and closed-loop systems; biosensors, microarrays, and lab-on-a-chip; wearable electronics; biomedical SoCs;

  • 3D-IC Design & Packaging

  • Analog, Mixed-Signal & RF Circuits and Systems

  • SOI vs. CMOS for Analog & Digital Circuits

  • CPU/DSP/GPU Cores

  • High-Performance IO Sub-Systems & Interconnects

  • Foundry Services & Technologies

  • Novel CMOS Design Techniques

  • EDA Tools, Algorithms, and Tool Usage

  • Design Methodologies, Techniques, and Technologies for All Aspects of Electronic Circuits

  • FPGA-Based Designs, Tools, and Applications

  • Wireline and Wireless Communication Circuits and Systems

  • Static, dynamic, and non-volatile memories for stand-alone and embedded applications

  • Memory/SSD controllers

  • High-bandwidth I/O interfaces

  • Memories based on phase-change, magnetic, spin-transfer-torque, ferroelectric, and resistive materials

  • Array architectures and circuits to improve low-voltage operation

  • Power reduction, bit-error management, reliability, and fault tolerance; memory-subsystem enhancements, including in-memory logic functions

  • Green Circuits, Systems, and Design Methodologies

  • Embedded Memory Technologies & IPs

  • Logic Synthesis and Circuit Optimization

  • Timing and Circuit Analysis and Circuit Optimization

  • Receivers/transmitters/transceivers for wireline systems, including backplane transceivers, optical links, chip-to-chip communications, 2.5/3D interconnect

  • IC & IP Design

  • SiP and Innovative Packing Techniques

  • Network-on-Chip (NoC) & System-Level Communication & Interconnects

  • Special-purpose digital circuits, intra-chip communication circuits

  • Clock-distribution techniques, soft-error and variation-tolerant circuits; Circuits for power management in digital applications

  • Emerging IC and system solutions for: biomedical applications, sensor interfaces,

  • Circuit Simulation and Interconnect Analysis

  • Timing Analysis and Design for Manufacturability

  • Physical Design and Manufacturability

  • Power Analysis and Low-Power Design

  • Validation, Test Planning, Testing and Coverage

  • Formal Verification

  • Signal Integrity and Design Reliability

  • System-Level Design and Co-Design

  • High-Level Synthesis

  • Physical Synthesis Tools and Techniques

  • Low-Power SoC Platforms

  • Cost-Effective SoC-Based Platform Solutions

  • Embedded Software, Tools and Design

  • Embedded Design and Platforms

  • Floor-Planning

  • Beyond Die-Integration and

  • Package/Hybrid/Board Design

  • Novel Software Architecture for Multicore SoCs

  • System Level Design Methodology, EDA and Design Tools for SoC

  • Signal Integrity, Design for Testability, and Design Verification

  • Design for Manufacturability, Variation-Aware Methodologies

  • Emerging Specialized Design Technologies

  • Manufacturing Test and Silicon Debug


In addition to conventional SoC-related topics, the SoC Conference invites proposals for topics for individual Tracks, Panels, Workshops and Tutorials.






The SoC Conference provides a series of unique sponsorship opportunities for participating companies interested in promoting their names, logos, and brands and their products and technologies to a very targeted and interested audience

To receive a complete listing of all available sponsorship opportunities, please contact or call us at 949-981-1837. We will be more than happy to customize our sponsorship packages to meet your budget and your marketing objectives.

SoC Conference Platinum and Gold sponsors’ logos will be displayed on the SoC Conference main page as well as on the Savant Company Web page until two weeks after the Conference. Sponsors’ logos are always displayed on the SoC Conference public archives page. Our Platinum and Gold sponsorship packages include Tabletop Exhibit opportunities, several complimentary Conference passes, and a variety of promotional opportunities. For specific sponsorship details, please contact   









The SoC Conference Tabletop Exhibit is an outstanding, inexpensive forum for your Sales, Marketing, and Applications Engineering teams, allowing them to meet face-to-face with design engineers attending the Conference or visiting the Tabletop Exhibit.


To reserve your Tabletop Exhibit space please contact  SoC Conference Tabletop Exhibit provides several free full conference passes as well as a series of outstanding promotional opportunities for the exhibiting companies. Please contact us for more information and to receive the Tabletop Exhibit application/contract.







Track and Session Presenters, Keynote Speakers, and Panel Members who can contribute their professional expertise have a wonderful opportunity to share their innovative SoC, ASIC, ASSP, FPGA, eFPGA, and Foundry-related technology or products at this event to a very focused and targeted audience.

Technical presentations are invited that address new and previously unpublished results on System-on-Chip topics and related areas (as listed above). 


To explore speaking opportunities at the 16th International SoC Conference, for information on our Tabletop Exhibit, or to develop highly targeted Workshops, please contact the SoC Conference Organizing Committee at:   or   949-981-1837








Presentations at the International System-on-Chip (SoC) Conference are in the form of 30-minute talks with PowerPoint slides. Presentation slides will be published in the SoC Conference Proceedings. Participants are not required to submit written papers, but a select group will be invited to submit a paper for inclusion in the SoC Conference Proceedings.

Submissions must include a title, abstract (1-2 paragraphs in MSWord), and the presenter's contact information (name, affiliation, job title, bio, address, phone, fax, and email). Please indicate whether you have submitted, intend to submit, or have already presented or published a similar or overlapping submission to another conference or journal. Also indicate if you would like the submission to be held confidential.

Submissions are evaluated by the SoC Conference Organizing Committee and the SoC Technical Advisory Board on the basis of the overall complexity of the technology or device, the degree of innovation, the incorporation of advanced technology, the potential market significance, and most importantly, the anticipated interest to the audience. Research and software proposals will be evaluated by similar criteria. If you are describing a product, you must indicate its status: its design, development, tape out, silicon, shipping, etc.

Please submit your abstract in MSWord to:  

Submissions containing figures may be submitted in .pdf, but plain ASCII text or MS Word is preferred.



Don't Miss Out!


Please submit your proposed Abstract & Bio ASAP

for SoC Conference Organizing Committee & Technical Advisory Board

Review and Consideration.



Questions    or   949-981-1837





Attendee demographics for past SoC Conferences (based on job responsibilities):

  • 62% SoC & ASIC Designers, Design Engineers, System Architects, and Engineering Management

  • 23% University Engineering Professors and Engineering Students

  • 9% Technical Marketing, Sales, or Business Development Management

  • 4% Media, Strategic Planning, and Analysts

  • 2% Other














JRI Technology



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If you have any questions or need more information, please contact:
Thank you!





International System-on-Chip (SoC) Conference Technical Advisory Board



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