The 15th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

 October 18 & 19, 2017

University of California, Irvine (UCI) - Calit2


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15th International System-on-Chip (SoC)

Conference, Exhibit & Workshops


The Theme for This Year’s Conference Is “Secure and Intelligent Silicon Systems for Emerging Applications."


To present and/or exhibit at this highly-targeted International System-on-Chip (SoC) Conference, please contact: 

949-981-1837 or



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Directions & Parking for Calit2 Building at the University of California, Irvine (UCI)


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Schedule & Program Summary




SoC Conference Day 1

Wednesday, October 18, 2017

UCI - Calit2 Building

  8:30 am - 6:00 pm



SoC Conference Day 2

Thursday, October 19, 2017

UCI - Calit2 Building

  8:30 am - 6:00 pm



SoC Tabletop Exhibit & Reception

Wednesday, October 18, 2017

UCI - Calit2 Building

  2:00 pm - 7:00 pm














Jim Aralis, Chief Technology Officer (CTO), and Vice President of R&D.


“What does a SoC look like in 2025? Who, what and Why”



Abstract:  The talk will focus on changes in technology, applications, and economics of the SoC ecosystem, and what it will likely mean for the realization of these devices in the next decade. It will examine the way process technology, packaging technology, design abstraction, and other such factors of true differentiation will push these core devices. These observations are intended to provide insights into where to position your company and career for the coming decade.


Bio: Jim Aralis has served as chief technology officer and vice president of R&D for Microsemi since January 2007. He has more than 30 years experience in developing custom analog device and process technologies, analog and mixed-signal ICs and systems, and CAD systems.  Jim played a key role in transitioning Microsemi to a virtually fabless model, supporting multiple process technologies including, high voltage and high power BCD/CMOS, high power high integration CMOS, GaAs, SiGe, IPD, RF CMOS SoI, GaN, SiC, and several high-density packaging technologies.  From 2000 to 2007, Jim established and served as senior design director of Maxim Integrated Product’s engineering center in Irvine, Calif. Before that, he spent 7 years with Texas Instruments/ Silicon Systems as mixed-signal design head and senior principal engineer. Additional experience includes 11 years with Hughes Aircraft Company in positions of increasing responsibility including senior scientist.  Jim earned a bachelor of science degree in Math Applied Science and Physics and a master of science in electrical engineering from UCLA. He holds 9 patents for circuit and system design.













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