The 17th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

 October 16 & 17, 2019

University of California, Irvine (UCI) - Calit2

         
 
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Keynotes & Panels

17th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

 

The Theme for This Year’s Conference Is “Silicon Engineering The Future."

 

 

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Click Here To Download The UCI Campus Map

Directions & Parking for Calit2 Building at the University of California, Irvine (UCI)

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Platinum Sponsors

 

 

 

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Schedule & Program Summary

 

 

 

SoC Conference Day 1

Wednesday, October 16, 2019

UCI - Calit2 Building

  8:00 am - 6:30 pm

 

 

SoC Conference Day 2

Thursday, October 17, 2019

UCI - Calit2 Building

  8:00 am - 6:30 pm

 

 

SoC Conference Tabletop Exhibit (open to public)

Wednesday, October 16, 2019

UCI - Calit2 Building

  10:00 am - 7:00 pm

 

 

SoC Student Design Contest & Reception at 5:30 pm (open to public)

Wednesday, October 16, 2019

UCI - Calit2 Building

  2:00 pm - 7:00 pm

 

 

 

 

 

 

 

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Intel

 

 

Keynote

 

 

 

 

Sailesh Kottapalli, Intel Senior Fellow, Intel Architecture, Graphics and Software Chief Architect, Datacenter Processor Architecture.
 

 

“TBD"

 

 

Abstract: TBA.

Bio: Sailesh Kottapalli, Intel Fellow, Platform Engineering Group Director, Data Center Processor Architecture, joined Intel in 1996 as a design engineer working on the first Intel® Itanium® processor, then code-named "Merced." Subsequently, he served as lead engineer for several Intel Itanium and Intel Xeon processor evaluations, and more recently, as lead architect for a series of Intel Xeon server processors. His work in this area earned Kottapalli an Intel Achievement Award for delivering record generational performance improvements in a high-end server product. An active participant in industry and internal conferences, Kottapalli has authored or co-authored several published technical papers, delivered talks and taken part in roundtables and panel discussions. He has also been granted approximately three dozen patents in processor architecture, with additional patents pending. Kottapalli holds a bachelor's degree in computer science from Andhra University in India and a master's degree in computer engineering from Virginia Tech.
 

 

 

 

 

 

University of Texas at Austin

 

 

Keynote

 

 

 

 

 

 

Dr. Lizy Kurian John, P.E., The Cullen Trust for Higher Education Endowed Professor in Engineering No.3, IEEE Fellow., University of Texas at Austin.
 

"TBD"

 

Abstract:  TBD. 

 

Bio: Dr. Lizy Kurian John holds the Cullen Trust for Higher Education Endowed Professorship in Electrical Engineering in the Department of Electrical & Computer Engineering at The University of Texas at Austin. She received her Ph.D. in computer engineering from The Pennsylvania State University. She joined The University of Texas Austin faculty in 1996. Her research is in the areas of computer architecture, multicore processors, memory systems, performance evaluation and benchmarking, workload characterization, and reconfigurable computing. Professor John's research has been supported by the National Science Foundation, Semiconductor Research Consortium (SRC), DARPA, Lockheed Martin, AMD, Oracle, Huawei, IBM, Intel, Motorola, Freescale, Dell, Samsung, Texas Instruments, etc.. She is recipient of NSF CAREER award (1996), UT Austin Engineering Foundation Faculty Award (2001), Halliburton, Brown and Root Engineering Foundation Young Faculty Award (1999), University of Texas Alumni Association Teaching Award (2004), The Pennsylvania State University Outstanding Engineering Alumnus (2011) etc. Professor John holds 10 U. S. patents and has published 16 book chapters, 200 refereed journal and conference publications, and approximately 50 workshop papers. She has coauthored books on Digital Systems Design using VHDL (Cengage Publishers), Digital Systems Design using Verilog (Cengage Publishers) and has edited a book on Computer Performance Evaluation and Benchmarking (CRC Press). She has also edited three books on workload characterization. Professor John is the Editor-in-Chief (EIC) Elect of IEEE MICRO (term begins January 2019) and she is in the editorial boards of ACM Transactions on Architecture and Code Optimizations (TACO), IEEE Computer Architecture Letters, IEEE Transactions on Sustainable Computing, and has served in the past as an associate editor of IEEE Transactions on Computers and IEEE Transactions on VLSI. She is a member of IEEE, IEEE Computer Society, ACM, and ACM SIGARCH. She is an IEEE Fellow (Class of 2009).

 

 

 

 

 

Xilinx

 

 

Keynote

 

 

 

 

 

 

Jennifer Wong, Vice President of FPGA Product Development. Xilinx Inc.
 

 

"TBD"

 

Abstract: TBD.


Bio: TBD.

 

 

 

Panel Info

 

 Wednesday, October 17, at 5:00

Panel #1. . . Coming Soon

 

 

 

 

 

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