The 15th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

 October 18 & 19, 2017

University of California, Irvine (UCI) - Calit2

         
 
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15h International System-on-Chip (SoC)

Conference, Exhibit & Workshops

 

The Theme for This Year’s Conference Is “Secure and Intelligence Silicon Systems for Emerging Applications."

 

To present and/or exhibit at this highly-targeted International System-on-Chip (SoC) Conference, please contact: 

949-981-1837 or SoC.Conf.Update@Gmail.com

 

 

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Day One Wednesday October 18, 2017

 

SoC Conference Program Agenda*

 

 

Savant Company Inc.

 

Farhad Mafie, SoC Conference Chairman.

 

 

Welcome and Opening Remarks, Technology/Market Trends.

 

 

Farhad Mafie is SoC Conference Chairman. He has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience. He is the former Vice President of Marketing and Engineering at Toshiba Semiconductor. He has also worked in strategic marketing, project and design engineering at Lucent Technologies, Unisys, and MSI Data. Farhad has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton. He is an author and a translator, and his articles have been published in a variety of journals and Web-based magazines on technology and political affairs. In 2003, he published the biography of Iranian poet and Nobel nominee who lived in exile, Nader Naderpour (1929-2000), Iranian Poet, Thinker, Patriot. Farhad is also Editor-in-Chief for the CRC Press SoC Design and Technologies Book Series, which includes (1) Low-Power NoC for High-Performance SoC Design and (2) Design of Cost-Efficient Interconnect Processing Units. Farhad is an active member of IEEE, and he is the chair of IEEE Orange County Solid-State Circuits Society (SSCS), as well as IEEE Orange County Entrepreneurs' Network (OCEN). He is also a member of two UCI Advisory Committees: Communication System Engineering and Embedded System Engineering Certificate Programs. 

     

 

UC Irvine

 

Dr. Michael J. Klopfer, Technical Director, CalPlug - California Plug Load Research Center, California Institute for Telecommunications and Information Technology (Calit2), University of California, Irvine.


 

“University Collaboration for Electronics Education."   

 

Abstract: For electronics component and solutions manufacturers, interfacing the educational environment can be a challenge. In this presentation, we will share experiences from within the university based on working with undergraduate and graduate students as well as professional researchers to help understand the barriers to effective uptake of demonstration and education focused products.

 

Bio:  Michael is doctoral graduate in biomedical engineering. He has a background in consumer electronics and power systems, and has designed and constructed high-load power supplies and power management systems for x-ray generators. He has also led numerous projects related to the planning and installation of power, data and low voltage interface lines and assisted in the installation and upgrade of factory automation systems.
 

 

 

 

 

 

 

 

EPIC semiconductors

 

 

 

Wolf Richter is the company's president, EPIC semiconductors.
 

 

“Alma-Mater-on-Chip: nanoCloudProcessors (nCPs) reverse Moore's law.”

 


Abstract: TThere is no question that the microprocessor has changed the world. But approaching its limits, it has become increasingly difficult to enhance its performance further. The reason: it’s increasingly challenging to overcome "Moore's Law". Doubling transistor functions, and reducing the chip price with no successor in sight, until now!

A nanoCloudProcessor (nCP) is literally a dust-sized device. It has been designed well over a decade and its not bounded by "Moore's law”. It was created to overcome the major challenges facing today's semiconductors: Cost, Power, Complexity, Microwave, Distraction and Inherent Artificial Intelligence. A single nanoCloudProcessors is 40um/side. 200,000 of them can be combined as an array with the size /price of a modern 50-cent micro-controller, allowing 20 billion operations per second at 100KHz. Wolf will demonstrate some features of an nCP live on stage.

Bio: Wolf Richter is the company's president for EPIC semiconductors. Both entrepreneur and inventor, he is devoted to pioneering communication technologies and services. He has more than three decades of technology development experience and has an outstanding track record of economical innovations. Wolf has authored more than 150 patents and won awards at Expo 2000 - Austria Microsystems 2005 and Echelon 2007. His innovations has also led to the German Economy Award for Best Innovation and an Ernst & Young entrepreneurship award in 2007.
 

 

 

 

 

 

 

 

Synopsys

 

 

Manmeet Walia, Senior Product Manager for Mixed-Signal PHY IP, Synopsys.

 

 

“25G Interconnect Solution for New Wave of Computing/Networking SoCs.” 

 

Abstract: The tremendous amount of bandwidth increase is the byproduct of the new wave of high-performance computing/networking applications including big data analytics, machine learning, network functions virtualization (NFV), wireless 4G/5G, in-memory database processing, video analytics & network processing. The performance of SoCs for these applications must maintain their robustness as the voltage and temperature conditions vary in harsh data center environments. For this reason, designers are leveraging high speed, high-performance, low latency and low-power multi-protocol interface IP solutions to access interconnects that complement higher CPU processing power, and provide the necessary capabilities for power, performance, and area tradeoffs. Designers also turn to configurable RTL to implement a growing percentage of their design ensuring their product is optimized for its targeted application. In this presentation, we will highlight semiconductor and IP market trends in next-generation SoCs for emerging computing/networking applications. We will also describe the advantages of leveraging high-speed interface IP that supports various high-speed industry-standard interconnect protocols like PCI Express, Ethernet and CCIX.
 

Bio: Manmeet Walia is a Senior Product Manager for Mixed-Signal PHY IP at Synopsys. He brings more than 15 years of experience in product marketing, product management and system engineering covering ASSP, ASIC, and IP products for broad range of applications. Manmeet holds a Master of Science degree in Electrical Engineering from University of Toledo, and an MBA from San Diego State University.
 

 

 

Morning Break

Morning Break

 

 

Microsemi

 

 

 

Dr. Rino Micheloni is Engineering Fellow at Microsemi Corporation.

 

 

“Flash Controllers for SSD’s Lifetime Extension through Machine Learning.”

 


Abstract:  The advent of 3D Flash memories introduced significant issues in terms of characterization and system-level optimization that can be performed to increase memory’s reliability over time. In this work we show how machine learning algorithms can help designers to improve 3D reliability. Experimental results based on TLC 3D NAND devices will be used to demonstrate the effectiveness of machine learning in the context of Flash memories.

Bio: Dr. Rino Micheloni is Engineering Fellow at Microsemi Corporation where he currently runs the Non-Volatile Memory Lab in Milan, with special focus on NAND Flash. Prior to joining Microsemi, he was Fellow at PMC-Sierra, working on NAND Flash characterization, LDPC, and NAND Signal Processing as part of the team developing Flash controllers for PCIe SSDs. Before that, he was with IDT (Integrated Device Technology) as Lead Flash Technologist, driving the architecture and design of the BCH engine in the world’s 1st PCIe NVMe SSD controller. Early in his career, he led NAND design teams at STMicroelectronics, Hynix, Infineon, and Qimonda; during this time, he developed the industry’s first MLC NOR device with embedded ECC technology and the industry’s first MLC NAND with embedded BCH. Rino is IEEE Senior Member, he has co-authored more than 50 publications, and he holds 242 patents worldwide (including 120 US patents). He received the STMicroelectronics Exceptional Patent Award in 2003 and 2004, and the Qimonda IP Award in 2007.
Rino has published the following books with Springer: 3D Flash Memories (2016), Inside Solid State Drives (2013), Inside NAND Flash Memories (2010), Error Correction Codes for Non-Volatile Memories (2008), Memories in Wireless Systems (2008), and VLSI-Design of Non-Volatile Memories (2005).

 

 

 

Intel

 

 

Keynote

 

 

Cormac Brick, Director of Machine Intelligence, Movidius Group, Intel Corporation.

 

Keynote:  “Designing for Deep Learning Inference in Power Constrained Environments.

 

 

Abstract:  TBD.

 

Bio: Cormac Brick is Director of Machine Intelligence in the Movidius group at Intel Corporation, where he builds new foundational algorithms for computer vision and machine intelligence to enhance the Myriad VPU product family. Cormac contributes to internal architecture, and helps customers build products using very latest techniques in deep learning and embedded vision through a set of advanced applications and libraries. Cormac has worked with Movidius since its early days and has contributed heavily towards the design of the ISA, hardware systems design, computer vision software development and tools. Cormac has a B.Eng. in Electronic Engineering from University College Cork.

 

 

 

Lunch

Lunch

 

 

 

 

Microsemi

 

 

Keynote

 

 

 

 

Ted Speers, VP and Head of Product Architecture and Planning for Microsemi SoC Group.

 

 

Keynote: “RISC-V Challenges and Possibilities.”
 

 

Abstract:  TBA

 

Bio: Ted Speers is Head of Product Architecture and Planning for Microsemi’s SoC Group, responsible for defining their roadmap for low power, secure, reliable FPGAs and SoC FPGAs. He joined Microsemi in 1987 and held roles in process engineering and product engineering before assuming his current role in 2003. He is a Technical Fellow and co-inventor on 35 US Patents. Prior to joining Microsemi, he worked at LSI Logic. Ted has a BS in Chemical Engineering from Cornell.

 

 

 

 

 

 

 

SiFive

 

 

Jack Kang, VP of Product and Business Development, SiFive

 

 

“Introducing the New RISC-V U54 Coreplex.” 

 

 

Abstract: In this presentation, SiFive, a founding member of the RISC-V Foundation, will introduce the U54 Coreplex, a multi-core 64-bit application-processor-class RISC-V CPU. The new design supports a quad-core configuration featuring a coherent L2 cache, support for the latest RISC-V specifications (including RV64GC, machine, supervisor, and user privilege modes), and external debug support. The new CPU supports Linux, Unix, FreeBSD, and other advanced operating systems in the RISC-V ecosystem.
 

Bio: Jack is currently Vice President of Product and Business Development at SiFive. Prior to SiFive, Jack held a variety of senior business development, product management, and product marketing roles at both NVIDIA and Marvell, with a long track record of very successful, large scale design wins. Jack started his career as a frontend design engineer, with a focus on CPU architecture and design. Jack received his BS degree in Electrical Engineering and Computer Science from UC Berkeley.

 

 

 

 

 

 

 

 

Imperas Software Ltd.

 

 

Larry Lapides, VP, Imperas Software Ltd.

 

 

“RISC-V Models and Simulation Enable Early Software Bring Up.” 

 

 

Abstract: As RISC-V processor cores start to be designed into new SoCs, software requirements need to be considered. One of the issues with moving to RISC-V based SoCs is porting operating systems, drivers, firmware and applications from existing platforms. Can this be easily accomplished? Can it be accomplished, in the majority, before silicon is available? Virtual platforms, or software simulation, can help accelerate this porting and bring up process. Virtual platforms provide a near real time software simulation environment for executing the actual software binaries, plus have full debug, analysis and test tools.  Now there are not only models of RISC-V processor cores – generic RISC-V, SiFive, Andes; 32 and 64 bit cores – but also models of platforms running operating systems. These Extendable Platform Kits (EPKs) enable software engineers to quickly get started, months before any hardware, even FPGA prototypes, are available. For example, there is an EPK available of a Microsemi platform, using a SiFive E31 RV32-based core, running FreeRTOS. Virtual platform environments also enable the use of debug, analysis and test tools, not only for RISC-V, but in the case of a heterogeneous platform, supporting the multiple processors on the platform. Also, as Agile methods, including Continuous Integration Continuous Test (CICT) are adopted by embedded software teams, virtual platforms with their ease of automation enable this technology to be implemented. This presentation will provide a summary of the RISC-V processor models available through the Open Virtual Platforms (OVP) website (www.OVPworld.org), show a demo of the Imperas Microsemi E31/FreeRTOS EPK, and discuss the use of virtual platforms in accelerating migration to RISC-V based SoCs and improving software quality.
 

Bio: Larry currently runs worldwide sales and marketing at Imperas Software Ltd., and previously ran worldwide sales at EDA companies Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity’s IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before Verisity and SureFire Verification (acquired by Verisity), Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Larry was recently an Entrepreneur-in-Residence at Clark University’s Graduate School of Management, where he developed and taught a course on Entrepreneurial Communication and Influence. Larry holds a BA in Physics from the University of California Berkeley, a MS in Applied and Engineering Physics from Cornell University and a MBA from Clark University. Outside of high tech, Larry enjoys food and wine, and contributes to his wife’s website for wine region travel, ViciVino.com.

 

 

 

 

 

 

 

 

Codasip

 

 

Dan Ganousis, Director of NA Business Development, Codasip.

 

 

"A High-Level Design Methodology for RISC-V Processor Development." 

 

 

Abstract: High-level design methodologies have shown very promising results by producing better quality of results (QoR) as compared to RTL designs. However, high-level design methodologies have been very slow to be adopted by ASIC and SoC design teams because of their long learning curve and the significant expertise required to realize better QoR.  Codasip realized that high-level design methodologies were especially suited for targeted applications such as DSP, embedded processors, silicon security, and accelerators. This presentation will describe how Codasip has successfully implemented a high-level design methodology based on their CodAL language, Codasip Studio tool suite, and UVM verification flow to develop and verify their IoT and security RISC-V embedded processors.  Results will be shown from actual ASIC design projects comparing embedded processors developed in an RTL flow with manual creation of their software design kits (SDK) versus embedded processors created using Codasip’s high-level design flow. A RISC-V based processor designed by SecureRF that has been optimized to run IoT security applications will be described. The SecureRF RISC-V processor is based on Codasip’s Bk core with extensions and optimizations to allow single cycle processing of key aspects of SecureRF’s security algorithms, without requiring changes to the existing software infrastructure. Results from a recent Microsemi audio processor design will also be shown where optimizing at the architectural level by adding DSP extensions to the RISC-V ISA improved performance by over 56x compared to their previous design that used an ARM embedded processor that could not be modified or optimized.
 

Bio: Dan Ganousis has over 40 years of experience in the EDA and semiconductor IP industry. He began his career working on processors at Zilog (Z80), NCR (65c02), Digital (MicroVax) and Solbourne Computer (Sparc KAP). Dan previously served as CEO of AccelChip and Arithmatica, and was on the executive staff of Oasys Design, Cyclos, Innoveda, VeriBest, Viewlogic, and Mentor Graphics. Dan currently oversees North American business development at Codasip where he manages marketing, sales, and field application engineering.
 

 

 

 

 

 

 

 

Dover Microsystems.

 

 

Steven Milburn, Chief Technical Officer, Dover Microsystems.

 

 

“The Dover PIPE: Processor Interlocks for Policy Enforcement.” 

 

Abstract: Preventable cyber security breaches are affecting governments, businesses, and individuals around the world every day. These breaches exploit errors in software stacks to gain access and control of devices. Cyber security today is centered around software solutions that have proven ineffective at preventing cyber attacks. Software consistently includes an average of 15 defects per thousand lines of code [1]. These defects provide open windows for hackers, and even the defensive cyber security software itself is inherently vulnerable. Dover has a different solution, a hybrid hardware-software solution, which can stop cyber attacks with hardware that understands and enforces software defined security policies.  Dover’s IP solution, PIPE (Processor Interlocks for Policy Enforcement), is the result of over 7 years and $31MM in government funding, starting with $25MM worth of DARPA CRASH SAFE program funding to create inherently secure processors that would be immune to the next Stuxnet [2]. Proof that the core architectural principles could be grafted onto a conventional processor extended with tags was presented at ASPLOS 2014 [3]. Draper Labs then continued the work to commercialize the results of the SAFE project, creating the first PIPE design and incubating Dover Microsystems until spinning Dover out as an independent company in July 2017.  PIPE is designed around a concept of metadata tagging, wherein every piece of code and data in the system has a corresponding metadata tag. These metadata tags are inspected upon every instruction retired by the processor to ensure they conform to all the policies installed on the SOC. These policies, and the meaning of the metadata, are defined in a software suite that runs in a secured fashion, either on an entirely separate core, or as a special execution mode of the host processor. Instructions are checked against these polices before any retired values are committed to the SOC. Therefore, PIPE can stop a violation, and hence an attack, before executing even a single instruction of the attack. Dover’s PIPE is designed to be an add-on block to any RISC-V processor core. It captures an instruction trace and all writes from the host processor, then checks each instruction against policies before committing writes to the system. This decoupled designed enables host processor to continue executing instructions in earnest when the PIPE experiences a delay in evaluating policies for an instruction, and enable the PIPE to catch up to the host processor by taking advantage of the pipeline bubbles in the host processor resulting from multi-cycle instructions, branches, or cache misses. The decoupled architecture also enables the PIPE design to have flexible mapping of data to metadata tags. It is possible to utilize fewer and/or smaller tags for various areas of memory, and to place tags into a protected addresses space not accessible by the host processor. To facilitate this decoupled elastic interface between the PIPE and host processor, a new interface definition is proposed for inclusion in RISC-V implementations that wish to connect to the PIPE. This new interface definition will enable a wide range of IP connections beyond Dover’s PIPE unit. Examples include the Debug Support Unit from the River CPU project, and tandem verification IP to compare Spike instruction traces to that of hardware.
References
[1]Writing Solid Code, Steve Maguire
[2] For more publications and talks from the CRASH SAFE project, see http://www.crash-safe.org/papers.html
[3] U. Dhawan, C. Hritcu, R. Rubin, N. Vasilakis, S. Chiricescu, J. M. Smith, T. F. Knight Jr, B. C. Pierce, and A. DeHon, “Architectural support for software-defined metadata processing,” ACM SIGARCH Computer Architecture News, vol. 43, no. 1, pp. 487–502, 2015.
 

Bio: Since joining the team in May 2016, Steven has led Dover’s design effort to build a secure microprocessor. As Chief Technical Officer, Steve draws on his experience as a System-on-Chip and microprocessor architect, as well as his program management and design leadership expertise, to drive innovation and shape Dover’s technical direction. Steve has been lead designer at two prior tech startups, both times bringing disruptive design to market success with first-pass silicon. As an SOC Architect at Microchip Technology, he was responsible for MIPS-based wireless microprocessor module designs, founded the Program Management group, and led the PIC32 design teams. Steve earned his BS in Computer and Electrical Engineering from the University of Rhode Island.

 

 

 

IHS Markit Technology

 

 

 

Robbie Galoso, Principal Analyst, Industrial Semiconductors, IHS Markit Technology.

 

 

"Industrial Semiconductors Market." 

 


Abstract: The industrial semiconductors market was worth $43.4 billion in 2016 or 12.3% of the entire semiconductor market. Industrial electronics spans a variety of application fields comprising manufacturing and process automation, test and measurement, medical electronics, building and home control, power & energy and military and civil aerospace. Industrial electronics is a large fragmented market with more than 100 semiconductor suppliers and around 50 of these companies earned more than $100 million from this segment in 2016. It is an exciting market since it typically provides higher margins than other semiconductor applications and the mid- to long-term demand for industrial electronics is expected to be robust: Factory automation will need more intelligence, as well as buildings to reduce their energy consumption and emissions. The medical electronics market will continue in its goal to benefit an increasingly ageing population. Finally, growing demand in emerging countries for building infrastructure, industrial transportation and avionics will also drive the growth. Key Issues that will be addressed: What are the fastest growing segments. What are the key trends and regulations driving the market. Who are the suppliers and buyers of semiconductors for industrial electronics. What is the impact of the emerging BRIC countries growing demand. What are the opportunities for fast growing markets e.g. Digital Signage, smart thermostats, smart meters, LED lamps and digital video surveillance.

 

Bio: Robbie Galoso, Principal Analyst. Robbie specializes in market research with years of experience in primary and secondary research projects involving companies in the electronics industry. At IHS, Robbie manages the overall data quality of its semiconductor market share databases. Robbie’s research reports provide insights shaping the products and companies in the industrial electronics market which includes factory automation, security, energy, medical, military & aerospace segments. His responsibilities also include synthesis of worldwide economic trends to help generate accurate market forecasts. Robbie earned his Bachelor of Business Administration in International Business and Economics from Loyola Marymount University and MBA from Peter Drucker School of Management at Claremont Graduate University.

 

 

 

Afternoon Break

Afternoon Break

 

 

Panel

 

 

 

Panel:  

 

“Specialized Processors vs. General Purpose Cores: How to Achieve Performance Requirements for Emerging Applications (including AI, Deep Learning, Security, and Machine Intelligence).”

 

Moderator:  Farhad Mafie, SoC Conference Chairman.

Panelists: 

1. Cormac Brick, Director of Machine Intelligence in the Movidius Group, Intel Corporation.
2. Dr. Rino Micheloni is Engineering Fellow at Microsemi Corporation.
3. Jauher Zaidi, Chairman & Chief Innovation Officer, Palmchip Corporation.

4. Ted Speers, VP and Head of Product Architecture and Planning for Microsemi SoC Group.

5. Professor Eugenio Culurciello, Associate Professor, Electrical Engineering. Purdue University.
6. Abdullah Raouf, Sr. Product Marketing Manager, Lattice Semiconductor.



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Microsemi

 

 

 

Dr. Rino Micheloni, Engineering Fellow at Microsemi Corporation.

 

 

Panelist

 


Bio: Dr. Rino Micheloni is Engineering Fellow at Microsemi Corporation where he currently runs the Non-Volatile Memory Lab in Milan, with special focus on NAND Flash. Prior to joining Microsemi, he was Fellow at PMC-Sierra, working on NAND Flash characterization, LDPC, and NAND Signal Processing as part of the team developing Flash controllers for PCIe SSDs. Before that, he was with IDT (Integrated Device Technology) as Lead Flash Technologist, driving the architecture and design of the BCH engine in the world’s 1st PCIe NVMe SSD controller. Early in his career, he led NAND design teams at STMicroelectronics, Hynix, Infineon, and Qimonda; during this time, he developed the industry’s first MLC NOR device with embedded ECC technology and the industry’s first MLC NAND with embedded BCH. Rino is IEEE Senior Member, he has co-authored more than 50 publications, and he holds 242 patents worldwide (including 120 US patents). He received the STMicroelectronics Exceptional Patent Award in 2003 and 2004, and the Qimonda IP Award in 2007.
Rino has published the following books with Springer: 3D Flash Memories (2016), Inside Solid State Drives (2013), Inside NAND Flash Memories (2010), Error Correction Codes for Non-Volatile Memories (2008), Memories in Wireless Systems (2008), and VLSI-Design of Non-Volatile Memories (2005).

 

 

 

Intel

 

 

 

 

Cormac Brick, Director of Machine Intelligence, Movidius Group, Intel Corporation.

 

Panelist

 

Bio: Cormac Brick is Director of Machine Intelligence in the Movidius group at Intel Corporation, where he builds new foundational algorithms for computer vision and machine intelligence to enhance the Myriad VPU product family. Cormac contributes to internal architecture, and helps customers build products using very latest techniques in deep learning and embedded vision through a set of advanced applications and libraries. Cormac has worked with Movidius since its early days and has contributed heavily towards the design of the ISA, hardware systems design, computer vision software development and tools. Cormac has a B.Eng. in Electronic Engineering from University College Cork.

 

 

 

 

 

Microsemi

 

 

 

 

 

 

Ted Speers, VP and Head of Product Architecture and Planning for Microsemi SoC Group.

 

 

Panelist
 

Bio:Ted Speers is Head of Product Architecture and Planning for Microsemi’s SoC Group, responsible for defining their roadmap for low power, secure, reliable FPGAs and SoC FPGAs. He joined Microsemi in 1987 and held roles in process engineering and product engineering before assuming his current role in 2003. He is a Technical Fellow and co-inventor on 35 US Patents. Prior to joining Microsemi, he worked at LSI Logic. Ted has a BS in Chemical Engineering from Cornell.

 

 

Purdue University

 

 

 

Dr. Eugenio Culurciello, Associate Professor, Electrical Engineering. Purdue University.


 

Panelist

 

Bio: Eugenio Culurciello (S'97-M'99) received the Ph.D. degree in Electrical and Computer Engineering in 2004 from the Johns Hopkins University, Baltimore, MD. He is an associate professor of the School of Electrical and Computer Engineering, the Weldon School of Biomedical Engineering, the School of Mechanical Engineering, and of Psychological Sciences in the College of Health & Human Sciences at Purdue University, where he directs the ‘e-Lab’ laboratory. His research focus is in artificial vision systems, deep learning, hardware acceleration of vision algorithms. His research interests include: analog and mixed-mode integrated circuits for biomedical instrumentation, synthetic vision, bio-inspired sensory systems and networks, biological sensors, silicon-on-insulator design. Eugenio Culurciello is the recipient of The Presidential Early Career Award for Scientists and Engineers (PECASE), the Distinguished Lecturer of the IEEE (CASS), and is the author of the book "Silicon-on-Sapphire Circuits and Systems, Sensor and Biosensor interfaces" published by McGraw Hill in 2009, and "Biomedical Circuits and System, Integrated Instrumentation" published by Lulu in 2013. Info: https://engineering.purdue.edu/elab/ In 2013 Dr. Culurciello founded TeraDeep http://teradeep.com/, a company focused on the design of deep neural network processors. In 2016 Dr. Culurciello founded FWDNXT http://fwdnxt.com/, to deliver the next generation synthetic brains for artificial intelligence.
 

 

 

 

 

Lattice Semiconductor

 

 

 

 

 

 

Abdullah Raouf, Sr. Product Marketing Manager, Lattice Semiconductor.

 

 

Panelist
 

Bio: Abdullah Raouf is a senior product marketing manager for Lattice Semiconductor focused on FPGA and ASSP solutions for mobile markets. He has more than a decade of experience in semiconductor product management and holds a Bachelor of Science degree in Electrical Engineering from UC Davis and an MBA from Santa Clara University.

 

 

Palmchip

 

 

 

 

Jauher Zaidi, Chairman & Chief Innovation Officer, Palmchip Corporation.


 

Panelist.  

 

Bio: Jauher expert in Cyber Security, Storage and SoC design. He has over 33 years of experience in executive management and entrepreneurship. He helped start several hi-tech companies name a few, Palmchip, ESilicon, SandForce, Netvinci, and Moobila. He has written and presented a number of articles and papers on Cyber Security, SoC, IP business model, and future business and technology trends. He has also participated in many system-on-chip panels, and is a recognized expert in the area of SoC development. He invented the CoreFrame SoC memory centric Architecture. Which has enabled over 2 billion SoCs. He is a board of Adviser for Savant Company, a leader in International System-on-Chip conferences. He holds several patents on Cyber Security, SoC technology and infrastructure. The EE Times, a well-known industry publication, named him twice among the 'Top 20 visionary CEOs’ in the world. He is recipient of 2010 Terman Technology award for his Cloud computing innovation. He was 1st place award out of 34 cloud Applications.  Specialties: Startup, Entrepreneurship, Management, Financing, SoC Technology and Chip design, Sales and Marketing, Fund raising, Startups. IT outsourcing, Cloud Computing, Mobile (IPhone, Android) applications.

 

 

 

Networking

 

Tabletop Exhibit and Networking

 

 

   

Day TWO Thursday, October 19, 2017

 

SoC Conference Program Agenda*

 

 

Savant Company Inc.

 

Farhad Mafie, SoC Conference Chairman.

 

 

Welcome and Opening Remarks, Technology/Market Trends.

 

 

Farhad Mafie is SoC Conference Chairman. He has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience. He is the former Vice President of Marketing and Engineering at Toshiba Semiconductor. He has also worked in strategic marketing, project and design engineering at Lucent Technologies, Unisys, and MSI Data. Farhad has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton. He is an author and a translator, and his articles have been published in a variety of journals and Web-based magazines on technology and political affairs. In 2003, he published the biography of Iranian poet and Nobel nominee who lived in exile, Nader Naderpour (1929-2000), Iranian Poet, Thinker, Patriot. Farhad is also Editor-in-Chief for the CRC Press SoC Design and Technologies Book Series, which includes (1) Low-Power NoC for High-Performance SoC Design and (2) Design of Cost-Efficient Interconnect Processing Units. Farhad is an active member of IEEE, and he is the chair of IEEE Orange County Solid-State Circuits Society (SSCS), as well as IEEE Orange County Entrepreneurs' Network (OCEN). He is also a member of two UCI Advisory Committees: Communication System Engineering and Embedded System Engineering Certificate Programs. 

 

     

 

 

 

 

 

 

Infineon Technologies AG.

 

 

Pankaj Singh, Ranga Kadambi, Kiran Kumar Bandlamudi, Martin Ruhwandl, Infineon Technologies AG.

 

 

“Effective Qualitative Fault Injection Methodology to support failure mode analysis for ISO 26262 Automotive SoC.”  

 

Abstract: Fault injection simulation during pre-silicon verification shall confirm the effectiveness of the safety mechanisms to detect and control the relevant failure modes in the monitored safety function logic. A qualitative verification (i.e. confirmation of successful failure mode coverage by the safety mechanism) is required to ensure that the safety architecture considers all the potential failure modes. A more extensive statistical fault injection simulation campaign may be necessary, to determine the diagnostic coverage of the safety mechanism.  Fault injection simulation is performed using a design representation which accurately models the behavior and internal working of the relevant functional failure modes and safety mechanism (e.g. RTL code for digital logic). Faults may be injected into the safety function logic in several ways:
• Test pattern with erroneous input pattern or input values
• Manipulation of internal states and signals via dedicated fault injection modes and interfaces
• Manipulation of internal states and signals via the simulation environment (e.g. Fault Injection)
• Manipulation electrical parameters to force an erroneous behavior of the safety function
ISO26262 recommends fault injection as a verification technique to verify the safety mechanisms at various levels of the development flow including the verification analysis for the permanent, transient and multipoint faults. However the standard does not provide guidance on the details of implementation and execution.
In this presentation we share the Qualitative Fault Injection methodology to verify, confirm the detection and control of all relevant failure modes in the monitored safety function, existing limitations / pitfalls with methodology and the outlook. A common platform based approach is used to minimize the overall effort in extracting the fault sites and efficient traceability of the failure modes to the actual evidence and results.
 

Bio/s:

 

Pankaj completed his Bachelors in Electronics from NIT Bhopal in 1993; Master's in Electrical Engineering from USF, Florida and an MBA from SMU, Dallas. He has 20 years of industry experience which includes various leadership management roles. Currently he is leading Infineon’s Automotive SoC verification division in Singapore. He has published 28 technical papers in various international conferences.

Ranga Kadambi is currently working as Principal, Functional Safety verification in the Automotive, Microcontroller division of Infineon. Vast experience of greater than 19 years in semiconductor industry focusing on the RTL design, Verification and expertise in Automotive functional safety related verification aspects of the microcontroller development. Key interests include the definition of holistic methodologies to ensure the product is safe from systematic and random hardware faults.

Kirankumar has done his Masters in device physics from IIT Madras, India and Master of Science in IC design from Nanyang Technological University, Singapore. Broad experience of 16 years that covers product engineering, Test engineering, Design for Test and verification. Key interests includes fault

Martin Ruhwandl studied in electronic design and information technologies at the Technical University in Munich where he also did his PhD. After joining Infineon Technologies AG (Communication) in 1998 he moved to Lantiq (Wireline Communication), and went back to Infineon (Automotive) in 2013. He is working for close to 15 years in digital functional verification methodology and implementation, meanwhile as Principal engineer. Besides bottom up and system verification his main areas are of work is the random based, metric driven verification. For high quality verification with strong focus on reuse he developed and rolled out methodologies using ‘e’ as HDL on lower level and C/SystemC on higher level within Infineon teams. With this background he is now working on automotive IPs and SoC platforms where these methodologies have to be further improved and automated to hit the required safety standards (e.g. ISO 26262). The verification methodologies have been presented in several international conferences.
 

 

 

 

TSI Semiconductors.

 

 

 

 

 

 

 

 

Wilbur Catabay, SVP TDCS & Corporate Strategy, TSI Semiconductors.

 

 

"Integration and Development of Disruptive Materials in Domestic FAB Manufacturing."

 

Abstract:Over the past few years, there has been declining capability of domestic fabrication in North America. Most of the manufacturing has taking place in Asia with large foundries that only want to work with large integrated design manufacturers with large wafer volumes. This leaves a void for small to mid size IDM’s, Mil-Aero, and more importantly incubation start-up companies with innovative technologies targeting today's "Smart Markets". IDM’s and Entrepreneurs with new, smart architectures and novel disruptive materials are usually not accepted by more mainstream fabs, leaving them with precious few place to fabricate their technologies with secure IP retention. TSI Semiconductors will give an overview of how to close the gap that enables these disruptive technologies by way of novel materials and integration using CMOS platforms in a high volume manufacturing fab.
 

Bio: Wilbur Catabay is a veteran of the semiconductor industry with more than 25 years of experience. Recently, Mr. Catabay was VP of Technology at SVTC Technologies and prior President of Silicon Integrated Solutions, Inc., providing Engineering Services for Device and Process Integration. He also was Senior Director for LSI Logic’s Foundry Engineering & Integration organization and Director of the Advanced Process Module Development in the R&D organization. He was responsible for evaluating and developing advanced material research for CMOS transistors and advanced metal interconnect technology.  Mr. Catabay also worked with design and manufacturing organizations as the focal point for implementation of new process module technology from 130nm to 45nm CMOS technology nodes. In 1991, he was an assignee of the technical staff at SEMATECH. Mr. Catabay has submitted more than 100 invention disclosures and has been awarded more than 65 patents with patents pending during his tenure with LSI Logic and SVTC Technologies. He has published more than 50 technical articles in professional journals and presented at various technical conferences. In addition, he was the Patent Liaison and Inventor of the year at LSI Logic and currently serves as a board member/technical advisor for several technology firms. He attended San Jose State University in Industrial Technology with Business Management. During his spare time, Wilbur enjoys spending time with his family, including fishing and photographing nature.

 

 

 

QuickLogic

 

 

 

Dr. Timothy Saxe, CTO, QuickLogic.
 

 

“Embedded FPGAs – why now?"
 


Abstract:  Standalone FPGAs have thrived for 30 years, but previous efforts to commercialize embedded FPGAs all failed. So one has to ask: what has changed? Why will it be different this time?
There is not a single, simple answer. Instead a sea change involving multiple factors is creating the opportunity for embedded FPGAs to transform SOC designs. This change is part of the renewed understanding that Moore’s Law was not just about bigger, better, faster – instead it was about how to deliver functionality cost effectively. Bigger, better, faster was perfect for high volume, high value opportunities, but it is a stumbling block for fragmented cost sensitive wireless opportunities. This talk will show how embedded FPGAs help with the obvious challenges of increasing mask costs, increasing verification costs, and decreasing visibility into future needs, and also how embedded FPGAs help with some non-obvious challenges such as market consolidation.

Bio: Timothy Saxe (Ph.D) joined QuickLogic in May 2001 and has served as our Sr. Vice President and Chief Technology Officer since November 2008. Prior to this role, Dr. Saxe served as our Chief Technology Officer and Sr. Vice President, Engineering from August 2006 to November 2008 and as Vice President, Software Engineering from May 2001 to August 2006. From November 2000 to February 2001, Dr. Saxe was Vice President of FLASH Engineering at Actel Corporation, a semiconductor manufacturing company. Dr. Saxe joined GateField Corporation, a design verification tools and services company formerly known as Zycad, in June 1983 and was a founder of their semiconductor manufacturing division in 1993. Dr. Saxe became GateField's Chief Executive Officer in February 1999 and served in that capacity until GateField was acquired by Actel in November 2000. Mr. Saxe holds a B.S.E.E. degree from North Carolina State University, and an M.S.E.E. degree and a Ph.D. in electrical engineering from Stanford University.

 

 

 

Infineon Technologies AG

 

 

 

Author: Pankaj Singh, Sr. Manager SoC Verification, Infineon Technologies Singapore.

 

 

“Holistic System Level Approach - Convergence of Hardware and Software Verification to address Automotive SoC Challenges.“

 

 

 

 

 

Author: Martin Ruhwandl, Principal Engineers Functional Verification, Infineon Technologies AG.

 

 

 

Abstract: SoC especially Automotive design in general continues to grow in complexity. Advanced SoC verification methodologies can take care of systematic errors but are not sufficient to signoff Automotive designs. In Automotive SoC adherence to functional safety standards such as ISO 26262 has become an important consideration when defining the verification methodology. Fault tolerant hardware can be implemented in multiple ways. One approach taken to meet the safety requirements is to add redundancy; however this comes at additional cost and is not a practical solution. ISO26262 recommends fault injection as a verification technique to verify the safety mechanisms at various levels of the development flow. Fault injection aids in the discovery of new failure modes and ensuring the correctness and completeness of safety mechanisms implementation. While the tools and design flow are rapidly maturing to support safety compliant verification, there are still several gaps in meeting the overall functional verification requirements for Automotive SoC. In this presentation we share the safety verification methodology and flow overcoming some of these existing limitations with EDA tools and methodology without adding redundancy overhead.  The comprehensive safety verification approach encompasses fault injection at IP, subsystem and SoC. Besides statistical fault injection we also look at direct fault injection to give useful insight on specific safety mechanism. Careful examination is done to plan the strobing points and the time to maximize the effectiveness of direct fault injection in uncovering issues. The Safety Hardware itself is verified with high quality Safety library after the boot-up sequence. Novel approach on Bridging fault is implemented to overcome limitations of commercial EDA tools that use N-detect approach. Besides pre-silicon verification at IP, Subsystem and SoC this presentation also highlights the value of post silicon validation for safety. The completeness and correctness of the safety mechanisms implementation with respect to the hardware ‘Technical Safety Requirements’ is also done in post silicon validation. These Technical Safety Requirements are derived in accordance with Table 10 of ISO 26262. The complete verification methodology for Safety is requirement driven which uses exhaustive verification approach to find any systematic errors. It is fully automated to minimize run time or manual errors. The verification methodologies at pre-post silicon is successfully proven on multiple designs and has enabled adherence with the safety requirements as defined in ISO 26262 specification.
 

Bios:

Pankaj completed his Bachelors in Electronics from NIT Bhopal in 1993; Master's in Electrical Engineering from USF, Florida and an MBA from SMU, Dallas. He has 20 years of industry experience which includes various leadership management roles. Currently he is leading Infineon’s Automotive SoC verification division in Singapore. He has published 26 technical papers in various international conferences on design implementation-verification topics such as Synthesis, DFT, Analog IP integration and functional Verification.

Ranga Kadambi, currently working as a Manager, Functional Safety verification in the Automotive, Microcontroller division in Infineon. Vast experience of greater than 18 years in semiconductor industry focusing on the RTL design, Verification and expertise in Automotive functional safety related verification aspects of the microcontroller development. Key interests include the definition of holistic methodologies to ensure the product is safe from systematic and random hardware faults.”

Kirankumar has done his Masters in device physics from IIT Madras, India and Master of Science in IC design from Nanyang Technological University, Singapore. Broad experience of 15 years that covers product engineering, Test engineering, Design for Test and verification. Key interests includes fault models, fault simulations, fault tolerant architectures.

Martin Ruhwandl studied in electronic design and information technologies at the Technical University in Munich where he also did his PhD. After joining Infineon Technologies AG (Communication) in 1998 he moved to Lantiq (Wireline Communication), and went back to Infineon (Automotive) in 2013. He is working for close to 15 years in digital functional verification methodology and implementation, meanwhile as Principal engineer. Besides bottom up and system verification his main area are of work is the random based, metric driven verification. For high quality verification with strong focus on reuse he developed and rolled out methodologies using ‘e’ as HDL on lower level and C/SystemC on higher level within Infineon teams. With this background he is now working on automotive IPs and SoC platforms where these methodologies have to be further improved and automated to hit the required safety standards (e.g. ISO 26262). The verification methodologies has been presented in several international conferences.

 

 

 

Morning Break

Morning Break

 

 

Soitec

 

 

 

Dr. Christophe Maleville, Snior VP, Soitec Digital Electronics BU.
 

 

“Boost your SoC with Engineered Substrates.”
 



Abstract:  TBA.

Bio: Christophe Maleville has been appointed senior vice president of Soitec’s Digital Electronics BU in 2010.  He joined Soitec in 1993 and was a driving force behind the company’s joint research activities with CEA-Leti. For several years, he led new SOI process development, oversaw SOI technology transfer from R&D to production, and managed customer certifications. He also served as vice president, SOI Products Platform at Soitec, working closely with key customers worldwide. Maleville has authored or co-authored more than 30 papers and also holds some 30 patents. He has a PhD in microelectronics from Grenoble Institute of Technology and obtained an executive MBA from INSEAD.
 

 

 

Microsemi Corporation

 

 

 

 

Dr. Richard RAO, Microsemi Technical Fellow and a senior member of IEEE.

 

 

“FinFET Reliability Challenges and Design Mitigation.“

 

 

Abstract: In this presentation, we will review the challenging reliability issues related to the FinFET process. These include the Self Heating Effects on both the FEOL and BEOL failure mechanisms and TDDB issues on the Middle of Line. Design methodologies have been proposed to address these reliability issues.

Bio: Dr. Richard RAO is currently a Technical Fellow of Microsemi Corp, a lead supplier of high reliability integrate circuit, located in southern California, USA and a Senior Member of IEEE. He manages the design for reliability program and the main focus is to develop design for reliability flows for advanced circuits, packaging and chip to package interaction. He has a Ph.D. degree in solid mechanics of materials from the University of Science and Technology of China. Prior to joining Microsemi in 2004, Dr. Rao held various academic and technical positions in reliability physics and engineering. He was an associate professor at University of Science and Technology of China, a research fellow at Northwestern University, Evanston, IL, USA and National Science and Technology Board of Singapore. He also held senior and principal engineering positions in Motorola Electronics and Ericsson Inc. He has published over 30 papers on reliability physics and applications and also a main contributor of several JEDEC standards. He is a speaker to IRPS (International Reliability and Physics Symposium), ECTC (Electronics Component and Technology Conference), ISQED (International Symposium on Quality Electronics Design), ASME Symposiums and a keynote speaker to ICEPT and International Conf on System on Chip, etc. Dr. Rao has over 20 years hands on experience and knowledge in the advanced wafer processes such as 28nm HKMG and 16nm FF, advanced IC and optical packaging, chip to package interaction, board and system level reliability physics and applications. He has conducted professional development courses on advanced IC reliability to both industrial and academic worlds.
 

 

 

Lunch

Lunch

 

 

Purdue University

 

 

Keynote

 

 

Dr. Eugenio Culurciello, Associate Professor, Electrical Engineering. Purdue University.

@ Weldon School of Biomedical Engineering

@ School of Electrical and Computer Engineering

@ School of Mechanical Engineering

@ College of Health & Human Sciences


 

Keynote:  “Artificial Intelligence: past, present, future.?”

 

Abstract:  Deep Learning and neural networks are quickly becoming a dominant unified algorithm to extract information from unstructured data. Using standard gradient-descent learning algorithms and scalable models, they have been a revolution in image understanding, video summarization, captioning, scene understanding, speech recognition, text translation, and many more success stories coming on a almost daily basis! We will discuss how we can progress the field into more general artificial intelligence, so that these algorithms can continue to solve problems for us and take on more and more complex applications.

 

Bio: Eugenio Culurciello (S'97-M'99) received the Ph.D. degree in Electrical and Computer Engineering in 2004 from the Johns Hopkins University, Baltimore, MD. He is an associate professor of the School of Electrical and Computer Engineering, the Weldon School of Biomedical Engineering, the School of Mechanical Engineering, and of Psychological Sciences in the College of Health & Human Sciences at Purdue University, where he directs the ‘e-Lab’ laboratory. His research focus is in artificial vision systems, deep learning, hardware acceleration of vision algorithms. His research interests include: analog and mixed-mode integrated circuits for biomedical instrumentation, synthetic vision, bio-inspired sensory systems and networks, biological sensors, silicon-on-insulator design. Eugenio Culurciello is the recipient of The Presidential Early Career Award for Scientists and Engineers (PECASE), the Distinguished Lecturer of the IEEE (CASS), and is the author of the book "Silicon-on-Sapphire Circuits and Systems, Sensor and Biosensor interfaces" published by McGraw Hill in 2009, and "Biomedical Circuits and System, Integrated Instrumentation" published by Lulu in 2013. Info: https://engineering.purdue.edu/elab/ In 2013 Dr. Culurciello founded TeraDeep http://teradeep.com/, a company focused on the design of deep neural network processors. In 2016 Dr. Culurciello founded FWDNXT http://fwdnxt.com/, to deliver the next generation synthetic brains for artificial intelligence.
 

 

 

 

 

 

 

 

ARM

 

 

Marc Canel, Vice President of Security Systems at ARM Inc.

 

 

“The future of security systems in the Internet of Things marketplace.”

 

Abstract: In this session, we discuss how experience in the mobile world gave us an understanding of the required building blocks in the Internet of Things. The key concepts of isolation, root of trust, secure boot, robust encryption give us the mechanism that we take in the world of micro-controllers to protect against a range of attacks, from software to hardware. We discuss how use cases are impacted by new technologies, for example in the management of cellular subscriptions, in automotive.
 

Bio: Marc Canel has extensive experience in the mobile devices industry, driving software projects for the past 25 years, focusing on how mobile devices work with the Enterprise world. He is Vice President of Security Systems at ARM Inc for the past 3.5 years, leading the next generation of security architectures to become the foundation for Enterprise applications in a connected world. He promoted the definition of Trust systems and standards for devices in the Internet. He defined the architecture for the next generation Root of Trust for applications in devices. Prior to ARM Inc, he was Vice President of Software & Security Systems at Qualcomm where he spent 18 years, focusing on the features that make the products of Qualcomm more attractive to Enterprises. He led Qualcomm to become a leader in the area of content protection and privacy management. He also worked on the software ecosystem of Qualcomm, supporting the OEMs customers looking for complete solutions. Prior to Qualcomm, he was at IBM for 12 years where he had various roles in product development and management roles in data networking products.
 

 

 

Intrinsic ID

 

 

 

 

 

 

 

Dr. Pim Tuyls, Founder and Chief Executive Officer, Intrinsic ID.

 

 

"Authenticate Everything"
 

 

Abstract: As the Internet of Things approaches 50 billion devices with no slowing in sight, the flexibility to protect IoT devices at any point in the supply chain comes at an increasingly high cost because of limitations in traditional key delivery methods. In contrast, an SRAM-PUF-based approach offers flexibility and reduced cost without compromising security because, unlike traditional methods, with SRAM PUF-based key generation the root keys never leave the chip itself. This approach enables not only security management, but the flexibility to invoke that security in IoT endpoints at any point in the supply chain, at a cost appropriate to the use case.
 

Bio: Pim Tuyls is CEO of Intrinsic ID (www.Intrinsic-ID.com), a company specializing in IoT security technology. Before founding Intrinsic ID in 2008 he was at Philips Research, where he was Principal Scientist and managed the cryptography cluster. While there he initiated the work on Physical Unclonable Functions (PUFs), which forms the basis of Intrinsic ID’s silicon fingerprinting technology. Tuyls has a Ph.D. in mathematical physics from Leuven University, holds more than 50 patents and is widely acknowledged for his work in the field of security for embedded applications.

 

 

 

 

 

 

 

 

San Jose State University

 

 

Shahab Ardalan, PhD, San Jose State University

 

 

“Secure and Anti-Counterfeit Design.”

 

Abstract: In recent years, there has been a rapid innovation in the field of portable devices which has revolutionized the whole electronic market. The personalized gadgets such as smartphones are part of users’ life which contain sensitive data and private information. Privacy and protection of the data is a crucial task, consequently so many encryption techniques have been introduced to keep the data out of the hands of hackers. However, hackers employed new techniques that often proved the vulnerability of the crypto-processors. It is therefore imperative that system architects, circuit designers be aware of the security issue and be familiar with techniques to tackle such a rapidly growing threat. In light of the great importance to the new design dimension, security, this talk is proposed to provide an insight into and understanding of security challenges in design of digital circuits, identify the security requirements and present approaches leading to designing secure Cryptosystem-on-Chip (CoC).
 

Bio: Shahab Ardalan (IEEE M’02–SM’10) received his Ph.D. degree from University of Waterloo, Canada, in 2007. He joined the Analog & Mixed Signal R&D Group in Gennum Corp. (now Rambus) in 2007, where he continued his research activities on low-power, low-voltage circuits for high-speed data-communication. In 2010, he joined San Jose State University, CA, USA, as an endowed-chair assistant professor and the director of center for analog and mixed signal, where he is teaching and conducting research on topics of Analog & Mixed Signal ICs, mm-wave CMOS ICs, integrated circuit security and embedded systems. His research has led to more than 50 publications and patents. Dr. Ardalan was the IEEE Canada Central-Area Chair 2010-2011 and a member of IEEE Canada board of executive 2004-2011.  Dr. Ardalan is the recipient of the best paper award of ICUE’04, the CMC Industrial Award from strategic Microelectronic Council of ITAC in 2005, and the honorable mention award for “communication technology changing the world” in 2014 from IEEE Communications Society, as well as the best paper award for IRIC in 2016. He held a postgraduate scholarship from the National Science and Engineering Research Council of Canada (NSERC) from 2004 to 2007, and a NSERC Post-Doctoral Fellowship award in 2010. He has been a member of technical and organizing committees for more than 20 IEEE conferences.
 

 

 

Imagination Technologies

 

 

 

Majid Bemanian, Director of Segment Marketing for MIPS.
 

 

“Trust Management from Node to Cloud.“

 

 

Abstract: With the dawn of the Internet of Things (IoT) we are seeing a transition from previously closed platforms to open platforms. This introduces a number of challenges for manufacturers of products in ensuring reliable and secure management, monitoring and provisioning of services. The challenges are even greater for designers of medical devices, where the issues can be life and death. Manufacturers must build products that support OTA updates while also ensuring that the device is running the original manufacturer-installed software (anti-cloned) and that the platform is operating in the manufacturer’s intended state managed by the original software (not compromised during operation). It is vital that a chain of trust be established from silicon through to service provisioning to achieve mutual trust. Building a chain of trust requires multiple cryptographic touch points to be available, ensures the integrity and authenticity of the end devices, and ensures that there are linkages between the various aspects to stop malware or other subversive actors from compromising the digital exchange. We will discuss the “trust” stack that is needed to provide this end-to-end solution, including the APIs needed within embedded devices and touching on what’s needed in the network and server. We will also discuss a cross-industry open source effort to define the interface specification of the Trust Continuum to enable interoperability between the different components of the embedded device and cloud services.
 

Bio: Majid Bemanian is Director of Segment Marketing for MIPS, responsible for driving strategic security initiatives and leading market strategy for networking and storage. He also co-chairs the prpl Foundation’s security working group, focused on developing open standards and APIs around next-generation embedded security solutions. Mr. Bemanian was previously Director of Segment Marketing for Imagination Technologies for four years, and prior to that was Director of Marketing for the Processor Business Unit at AppliedMicro. He has more than 30 years of high-tech industry experience with hands-on engineering, marketing and business management skills. Bemanian has held key management positions with Amdahl Communications, Ascom-Timeplex, Encore Video, Raytheon Semi, LSI Logic, AppliedMicro and many early-stage startups. He holds several patents and a B.S. degree in Electrical Engineering from the University of Nevada, Reno.
 

 

 

prpl Foundation

 

 

 

Art Swift, President, prpl Foundation. 
 

 

“RISC-V and prpl: Why RISC-V could become the most secure embedded processor architecture."

Abstract: In this presentation, Art Swift, president of the prpl foundation, will describe current challenges in securing the IoT and a security framework to address these challenges developed by the members of the prpl Foundation. He will contrast the security offerings of the two leading embedded processor architectures, Arm and MIPS, and how they stack up against the framework. Swift will then assess whether the upstart, open source RISC-V ISA could become the ultimate winner for security in embedded applications.

 

Bio: Art Swift is president of the prpl Foundation. He has more than 20 years of executive-level experience in the tech industry, including CEO at low power chip-maker Transmeta (Nasdaq, TMTA), CEO of nanotech innovator Unidym, and vice president of marketing and business development at MIPS, a leading provider of microprocessor IP. Earlier in his career, Art was president of ISDCorp, a supplier of Linux engineering services to Fortune 500 companies; and chief operating officer for Lynuxworks, provider of the BlueCat Linux distribution and the LynxOS Linux-compatible real-time operating system. He also served in executive level positions for Cirrus Logic, a leading System-on-Chip supplier; and Sun Microsystems; one of the pioneering companies in networked computing and RISC processing.  Art holds a B.S. degree in electrical engineering from Pennsylvania State University. He is co-inventor of three U.S. patents. Art continues to serve as CEO of CUPP Computing AS, a European supplier of mobile security devices. He is also on the board of Numascale AS, a European supplier of affordable hardware solutions for big data applications, and the Foothill De Anza Foundation, an education-focused non-profit.  
 

 

 

Panel

"FREE"

Panel:  

 

“Security Issues and Challenges in The Next Generation of SoC Designs for Emerging Applications. Can You Make Cents of It?"

 

Moderator:  Farhad Mafie, SoC Conference Chairman.

Panelists:

1. Dr. Pim Tuyls, Founder and Chief Executive Officer, Intrinsic ID.
2. Marc Canel, Vice President, Security Technologies, ARM.
3. Louis Parks – President and CEO, SecureRF

4. Dr. Hoon Choi, Design Engineer Senior Director, Lattice Semiconductor.

5. Asaf Ashkenazi, Vice President, IoT security products, Rambus Security Division.

6. Michael Y. Chen, Director, Design for Security Business Unit, New Ventures Division, Mentor, A Siemens Business.


 

 

This Panel Is Open To Everyone . . .  Register Online for FREE Panel Pass

 

More Updates Coming Soon . . .

Several Opportunities to Win various Prizes During this Panel Discussion . . .

Don't Miss Out!

 

 

Savant Company Inc.

 

 

 

SoC Conference

 

 

 

 

 

 

 

Farhad Mafie, SoC Conference Chairman.

 

 

Moderator
 

Bio: Farhad Mafie is SoC Conference Chairman. He has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience. He is the former Vice President of Marketing and Engineering at Toshiba Semiconductor. He has also worked in strategic marketing, project and design engineering at Lucent Technologies, Unisys, and MSI Data. Farhad has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton. He is an author and a translator, and his articles have been published in a variety of journals and Web-based magazines on technology and political affairs. In 2003, he published the biography of Iranian poet and Nobel nominee who lived in exile, Nader Naderpour (1929-2000), Iranian Poet, Thinker, Patriot. Farhad is also Editor-in-Chief for the CRC Press SoC Design and Technologies Book Series, which includes (1) Low-Power NoC for High-Performance SoC Design and (2) Design of Cost-Efficient Interconnect Processing Units. Farhad is an active member of IEEE, and he is the chair of IEEE Orange County Solid-State Circuits Society (SSCS), as well as IEEE Orange County Entrepreneurs' Network (OCEN). He is also a member of two UCI Advisory Committees: Communication System Engineering and Embedded System Engineering Certificate Programs. 

 

This Panel Is Open To Everyone . . .  Register Online for FREE Panel Pass

 

More Updates Coming Soon . . .

 

Several Opportunities to Win various Prizes During this Panel Discussion . . .

Don't Miss Out!

 

     

 

 

ARM

 

 

Panelist

 

 

 

 

 

 

Marc Canel, VP security systems in ARM’s SW and Systems group.

 

 

Panelist

 

Bio: Marc Canel has extensive experience in the mobile devices industry, driving software projects for the past 25 years, focusing on how mobile devices work with the Enterprise world. He is Vice President of Security Systems at ARM Inc for the past 2.5 years, leading the next generation of security architectures to become the foundation for Enterprise applications in a connected world. He promoted the definition of Trust systems and standards for devices in the Internet. He defined the architecture for the next generation Root of Trust for applications in devices. Prior to ARM Inc, he was Vice President of Software & Security Systems at Qualcomm where he spent 18 years, focusing on the features that make the products of Qualcomm more attractive to Enterprises. He led Qualcomm to become a leader in the area of content protection and privacy management. He also worked on the software ecosystem management of Qualcomm, supporting the OEMs customers looking for complete solutions. Prior to Qualcomm, he was at IBM for 12 years where he had various roles in product development and management roles in data networking products.

 

 

 

 

Intrinsic ID

 

 

Panelist

 

 

 

 

 

 

Dr. Pim Tuyls, Founder and Chief Executive Officer, Intrinsic ID.

 

 

Panelist
 

Bio:   Dr. Pim Tuyls initiated work on Hardware Intrinsic Security™ within Philips Research in 2002. As a principal scientist, he managed the cryptography cluster in Philips Research in which the initial research was carried out. Later he transferred this work to Intrinsic-ID and headed the technology development.  Since 2004, Pim is a visiting professor at the COSIC institute of the Katholieke Universiteit Leuven. His inventions have resulted in numerous patents. He is widely accepted for his work in the security field and Hardware Intrinsic Security in particular.  Several of Pim’s papers relating to secure implementations of Physical Unclonable Functions (PUF) technology have been published at leading security conferences. He co-authored the book Security with Noisy Data, which was published by Springer in 2007.

 

 

 

SecureRF

 

 

Panelist

 

 

 

 

 

 

Louis Parks – President and CEO, SecureRF.

 

 

Panelist
 

Bio:   Mr. Parks is a co-founder of SecureRF, and serves as its President and Chief Executive Officer. He also serves on the company’s Board of Directors and its Chairman. Prior to joining SecureRF, Mr. Parks was the Senior Vice President of Marketing and Strategy for Global Logistics Technology, Inc. (“G-Log”), an innovative internet logistics company that was acquired by Oracle Corporation. For 10 years preceding G-Log, he was CEO/President of Client Technologies, Inc., a New York-based provider of Customer Relationship Management (CRM) applications for the financial sector that was acquired by a Canadian company. Mr. Parks also served as President of RKO/Warner Video where he was responsible for technology, operations and acquisitions throughout North America. Early in his career, he held both sales and engineering positions with IBM. Mr. Parks has consulted to Homeland Security on U.S. electronic border initiatives and has served as a resource to the White House on security issues related to the new electronic passports and passport cards. He is on the North American Board of AIM, the Association for Automatic Identification and Mobility, and is the former chairman of its RFID Experts Group (REG). He was on the Board of Advisors of the National Center for Aerospace Leadership (NCAL), a partnership between US industry, academia and government teams, and is currently an active member on the GS1/EPCglobal and US TAG ISO standards committees.
Mr. Parks holds a Bachelor of Commerce (with Honors) in Finance and Marketing from the University of Manitoba.

 

 

 

 

 

Lattice Semiconductor

 

 

Panelist

 

 

 

 

Dr. Hoon Choi, Design Engineer Senior Director, Lattice Semiconductor.

 

 

Panelist
 

Bio:  Hoon Choi is a Design Engineer Senior Director at Lattice Semiconductor, where he is involved in the spec and design of multiple generations of HDMI for the last 13+ years. Choi has led the design of HDCP 2.2 on the HDMI and compliance test spec. Additionally, he led the spec and implementation of UCP (China-CP) and the authentication implementation activity for Type-C. Prior to joining Lattice, Choi got his Ph.D from KAIST in Korea then began his career in the technology industry by working for Samsung Electronics, NeoPace Telecom, and Silicon Image which was acquired by Lattice.

 

 

 

 

Rambus

 

 

Panelist

 

 

 

 

Asaf Ashkenazi, Vice President, IoT security products, Rambus Security Division.

 

 

Panelist
 

Bio: Asaf Ashkenazi is a vice president for IoT security products at Rambus Security division. In this role, Asaf is responsible for the product definition, strategy and marketing of Rambus IoT security products. Asaf brings more than 15 years of security experience to the organization, spanning product management, business development and various engineering roles throughout his career. Prior to joining Rambus, Asaf oversaw product management for all of the security products at Qualcomm Technologies Inc. Asaf began his career at Motorola Semiconductor where he developed hardware security modules. Previously, Asaf served as Chief Security Architect at Freescale Semiconductor (now NXP), and has served as board member of the FIDO alliance. Asaf holds a Bachelor of Science in Electrical Engineering from Ben-Gurion University of the Negev, Israel, and has been granted 10 U.S. patents for security architectures and solutions.
 

 

 

 

 

Mentor, A Siemens Business

 

 

Panelist

 

 

 

 

Michael Y. Chen, Director, Design for Security Business Unit, New Ventures Division, Mentor, A Siemens Business.

 

 

Panelist
 

Bio:  Michael Chen is currently a Business Unit Director in the New Ventures Division at Mentor Graphics. As such, Michael manages leading-edge technology efforts for the company’s Design for Security initiative. Michael’s other positions during his more than 20 years at Mentor include serving as an account manager, field marketing manager for Asia Pacific, product line director for various products, and business unit director for SoC verifications products, with responsibility for HW/SW integration and electronic system-level design and verification solutions. Prior to joining Mentor, Michael was a senior consultant and field application engineer at Hewlett Packard and a logic simulator programmer for Xerox. He is a licensed Professional Engineer and holds several patents. He currently serves as Chair of the T3S TAB committee with the Semiconductor Research Corporation (SRC). Michael holds a B.S.E.E. and a B.S. in Information and Computer Science from the University of California, Irvine, graduating with honors. He is fluent in both Mandarin Chinese and Japanese and is well versed in both of those cultures.
 

 

 

 

 

Open To Everyone

 

Reception &  Networking

 

 

 

 

 

 

15th International SoC Conference Closed.

 

 

 

 

 

 

 

 

 

 

* * * * * * *

 

* SoC Conference Program is subject to change.  Savant Company Inc, SoC Conference Organizing Committee, and Technical Advisory Board, reserve the rights to revise or modify the SoC Conference agenda at its sole discretion.

 

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