The 17th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

 October 16 & 17, 2019

University of California, Irvine (UCI) - Calit2

         
 
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SoC Conference Presenters'

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17th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

 

The Theme for This Year’s Conference Is “Silicon Engineering The Future."

To present and/or exhibit at this highly-targeted International System-on-Chip (SoC) Conference, please contact: 

949-981-1837 or SoC.Conf.Update@Gmail.com

a

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Directions & Parking for Calit2 Building at the University of California, Irvine (UCI)

 

Platinum Sponsors

 

 

 

         

 

 

Schedule & Program Summary

 

 

 

SoC Conference Day 1

Wednesday, October 16, 2019

UCI - Calit2 Building

  8:00 am - 7:00 pm

 

 

SoC Conference Day 2

Thursday, October 17, 2019

UCI - Calit2 Building

  8:00 am - 6:30 pm

 

 

Tabletop Exhibition,

SoC Student Design Contest & Reception (at 6 pm) - Open to Public.

Wednesday, October 16, 2019

UCI - Calit2 Building

  2:00 pm - 7:00 pm

 
         

 

 

 

 

 

 

 

Day One Wednesday October 16, 2019

 

SoC Conference Program Agenda*

 

 

Savant Company Inc.

 

 

SoC Conference

 

Farhad Mafie, SoC Conference Chairman.

 

Farhad Mafie, President and CEO of Savant Company Inc., has over 25 years of experience in high-tech industries including semiconductor and computer businesses; additionally, he has more than 15 years of university-level teaching experience. A seasoned technical executive with extensive global experience in marketing, sales, and engineering. He enjoys developing business plan and go-to-market strategies for innovative and disruptive technologies, deal making, developing strategic alliances and partnerships.


In 2017, he became the CEO of Handycash Inc., a newly formed startup in Switzerland, developing an innovative mobile payment system based on Blockchain technology that will be launched in May 2020 in Germany.
 

For almost six years at Microsemi Corporation, as Vice President of Worldwide Product Marketing and Corporate Communications teams (in US, EU, India, and China), Farhad developed and managed the entire Microsemi’s worldwide outbound and inbound marketing strategies and programs; and worked directly with executive team on M&A projects and successfully integrating over 22 acquired companies.
 

Farhad is also the former Vice President of Marketing/Business Development and Technical Sales Engineering at Toshiba America Electronic Components, Inc. He was responsible for marketing the entire Toshiba standard ICs products in North America, as well as engineering development for Toshiba's Embedded and Digital Consumer products based on ASSP and SoC models.
 

Farhad has worked at Lucent Technologies on marketing communications ICs, Toshiba Information Systems on product definition for Toshiba's notebooks PCs and handheld products, Unisys on designing new processors and computer systems, Ocean Scientific on designing medical instrumentations, and MSI Data on designing data collection products. He has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton.
 

In 2003, Farhad designed, developed, and launched the annual Internationals System-on-Chip (SoC) Conference, Exhibits, and Workshops http://www.socconference.com. For two exciting days, this annual international Conference brings the most innovative and groundbreaking Chip-related technologies to its targeted audience. As the SoC Conference Chairman, he has driven the Conference leading-edge program at UC Irvine for the past 16 years.
 

In 2019, Blockchain Technology Summit was launched to bring the latest blockchain-related technologies, applications and startups in an exciting and educational Summit for worldwide audience http://www.blockchaintechnologysummit.com.
 

Farhad is an author and a translator. In 2003, he published the biography of Iranian poet and Nobel nominee who lived in exile, Nader Naderpour (1929-2000), Iranian Poet, Thinker, Patriot. Farhad is also Editor-in-Chief for the CRC Press SoC Design and Technologies Book Series, which includes (1) Low-Power NoC for High-Performance SoC Design and (2) Design of Cost-Efficient Interconnect Processing Units.
 

Farhad is a member of two UCI Advisory Committees: Communication System Engineering and Embedded System Engineering Certificate Programs. He is also the chair of IEEE Orange County Solid-State Circuits Society (SSCS), as well as IEEE Orange County Entrepreneurs' Network (OCEN).

 

     

 

GOWIN Semiconductor

 

 

David Grugett, Senior FAE Manager, Americas, GOWIN Semiconductor.


 

“IoT Device and Data Security for uSoC FPGAs at the Edge.”

 

 

Abstract: The extreme growth of IoT devices places new demand on microcontrollers and SoC feature requirements. IoT focused FPGAs have traditionally provided ways to fill processor portfolio gaps, but have historically lacked integration of the microprocessor and security engines to enable it as standalone edge solution. PUF (Physically Unclonable Function) technology enables devices to have a unique identity based on the intrinsic properties of a semiconductor device. Integrating this with a driver library for the Arm Cortex-M processor provides a root of trust for key generation, enabling device security and data encryption. Combined with factory provisioning, each device can be uniquely authenticated with a signed certificate from the manufacturer. The associated private key is generated at power up based on the PUF. This private key is never stored in flash and never leaves the device. Programmable fabric of an FPGA allows for interfacing, always on processing, and acceleration while a PUF based root of trust provides unclonable security to validate device firmware and encrypt data. Arm Cortex-M processors provide the ability to access PUF based encryption engines and FPGA fabric for communicating and processing data securely at the edge. These features combined provide IoT product developers unprecedented reductions in cost, power and product form factor going forward.

Bio: David Grugett is the Senior FAE Manager, Americas, for GOWIN Semiconductor focused on implementation of solutions for programmable technologies. He has over a decade of FPGA systems architecture and implementation experience in areas including ASIC prototyping, interfacing, bridging and edge connectivity. Mr. Grugett received his Bachelor of Science in Electrical Engineering from DeVry University.
 

 

 

Intel

 

 

Sujal A Vora, Senior Principal Engineer, Datacenter SoC Design Power and Performance Lead at Intel Corporation.

 

“Server SoC Power-Thermal Trends and Challenges.”
 

 

Abstract: This presentation will demonstrate Power and Thermal related challenges for future Intel server SoC designs. Server Thermal Design Power (TDP) continues to increase each product generation due to multiple factors including core count growth, IO growth, and performance demands. Even with process, design and architecture level improvements including Power management features, overall TDP growth comes with thermal and electrical challenges for both the CPU die as well as the platform. Presentation will highlight history and future of Server TDP, core count growth and the challenges that are ahead of us to incrementally improve socket level performance, per core performance, and performance per Watt over future generation of server products. On new technology and thermal side, presentation will highlight 3D stacking of active silicon and on-package 3D stacked memory (HBM) create major thermal challenges for an SOC to keep each die temperature under its reliability/functionality limits. Additionally, thermal challenge arises for Datacenter SoC as we shrink the die every process generation and add new architectural features plus new usage models with new workloads and application. Finally we will conclude with some mitigations and innovations in action.

Bio: Sujal earned his master’s degree in Electrical Engineering from Wright State University in 2000 and joined Intel the same year as design engineer for Itanium Processor. In his 18-year career span, Sujal has contributed to successful productization of more than 15 server CPUs for Intel. Sujal is currently a Director and Senior Principal Engineer at Intel in Silicon Engineering Group where he leads Power-Thermal-Binsplit and Power-performance for datacenter products. Beyond Intel, Sujal serves as a visiting faculty member at Stanford University, teaching masters classes on Silicon Debug and Power-Thermal-Binning concepts and industry application.
 

 

 

Morning Break

Morning Break

 

 

 

 

 

 

 

Intel

 

Keynote

 

 

 

Sailesh Kottapalli, Intel Senior Fellow, Intel Architecture, Graphics and Software
Chief Architect, Datacenter Processor Architecture.
 

 

“Computing Infrastructure in Data-Centric Era.”

 

 

Abstract: Computing infrastructure is increasingly influenced by the need to manage the exponential growth in data. The computing infrastructure needs to move this massive amount of data, store it and harvest it by processing for value added insights that drive business value by delivering to customer’s needs. This is driving changes across the entire spectrum of Computing, interconnects, memory and storage as well as security requirements. In addition, how we deliver that value across architecture, SW, design, process and packaging is also changing. This talk will outline a number of trends as a result and the specific solutions and SoC architecture to address these trends.


Bio: Sailesh Kottapalli, Intel Sr. Fellow, Chief Architect, Datacenter computing. Sailesh is a Senior Fellow at Intel. He is the chief architect for all the datacenter processors at Intel and leads the architecture for the Interconnect domain at Intel. He has over 23 years of contributions on the datacenter processors and has led the architecture for a number of highly successful Xeon processors.

 

 

 

Georgia Institute of Technology

 

 

 

Professor Arijit Raychowdhury, ON Semiconductor Junior Professor, Associate Professor, School of ECE, Georgia Institute of Technology.

 

 

“Discrete and Continuous Time Dynamical Systems for Solving Optimization Problems.”


Abstract: The explosion of big-data problems arising in statistics, machine learning (ML), image processing, 5G systems and other related areas have accelerated the development of hardware that rely on data-flow architectures and near-memory processing to address the memory-bottleneck. Looking beyond the success of neural network (NN) accelerators for classification, we recognize a growing need for solving complex optimization problems, which arise in all areas of signal processing such as ML model-training, computational imaging (medical, optical and hyper-spectral), resource-allocation in 5G massive MIMO networks and solving inverse problems such as LDPC decoding. In this talk, I will describe our recent work on hardware design for solving distributed optimizations. I will talk about the algorithmic foundations as well as circuit-architectures and programming models for solving large scale optimizations through local, iterative computation and near-neighbor communication. I will end the talk with our ongoing work on solving non-convex and combinational optimization problems and demonstrate certain analog, dynamical systems that have strong properties to solve such complex problems.

 

Bio: Arijit Raychowdhury is currently a Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology where he joined in January 2013. He is currently the co-director of the Georgia Tech Quantum Alliance. From 2013 to July 2019 he was an Associate Professor and held the ON Semiconductor Junior Professorship in the department. He received his Ph.D. degree in Electrical and Computer Engineering from Purdue University (2007) and his B.E. in Electrical and Telecommunication Engineering from Jadavpur University, India (2001). His industry experience includes five years as a Staff Scientist in the Circuits Research Lab, Intel Corporation, and a year as an Analog Circuit Researcher with Texas Instruments Inc. His research interests include low power digital and mixed-signal circuit design, design of power converters, sensors and exploring interactions of circuits with device technologies. His significant contributions to the semiconductor industry include the design of the world’s first adaptive echo-cancellation network for integrated DSLs (TI) and embedded world-line boosting for SRAM arrays (Intel). Dr. Raychowdhury holds more than 25 U.S. and international patents and has published over 170 articles in journals and refereed conferences. He has served on the Technical Program Committees of VLSI Symposium, CICC, DAC, ICCAD, ISLPED, DATE. He was the Associate Editor of the IEEE Transactions on Computer Aided Design from 2013-2018 and the Editor of the Microelectronics Journal, Elsevier Press from 2013 to 2017. He has also been a guest editor for multiple IEEE and ACM journals. He has also taught many short courses and invited tutorials at multiple conferences, workshops, industries and universities. He is the winner of IEEE/ACM Innovator under 40 award; the NSF CISE Research Initiation Initiative Award (CRII), 2015; Intel Labs Technical Contribution Award, 2011; Dimitris N. Chorafas Award for outstanding doctoral research, 2007; the Best Thesis Award, College of Engineering, Purdue University, 2007; SRC Technical Excellence Award, 2005; Intel Foundation Fellowship, 2006; NASA INAC Fellowship, 2004; the Meissner Fellowship 2002. He and his students have won eleven best paper awards over the years. Dr. Raychowdhury is a Senior Member of the IEEE.

 

 

 

 

 

 

TSMC

 

 

 

 

 

 

 

Dr. Paul Rousseau, Director of TSMC North America’s Field Technical Solutions.
RISC-V; is this the Linux of CPU’s?"

 

 

"TSMC’s great adventure into 7nm and beyond.”
 

Abstract: Moore’s law is getting ever more difficult, yet we keep upping the ante. This talk will describe how TSMC is leading into new territories with 7nm and beyond. Every generation now requires disruptive innovations to keep scaling and providing denser, faster and lower power technologies.

Bio: Paul Rousseau is Director for TSMC North America’s Field Technical Solutions where his team supports TSMC’s earliest technology adopters from technology definition to production. He has also held roles in enabling emerging customers, together with the VC community, bring disruptive technologies to the marketplace. Prior to TSMC, Paul worked as a process integration engineer in both CMOS and Bipolar technologies. He earned his Ph.D. and his Masters of Science Degree from Stanford University in Applied Physics.
 

 

 

Lunch

Lunch

 

 

Panel

 

 

 

Panel:


“RISC-V Realities, Opportunities and Challenges in the Complex and Crowded CPU Market.


Moderator: Farhad Mafie, SoC Conference Chairman.

Panelists:
1. Dr. Rob Aitken, R&D Fellow, ARM.
2. Nader Bagherzadeh, Professor (Joint Appointment), Electrical Engineering and Computer Science & Donald Bren School of Information and Computer Science. University of California, Irvine.
3. Martin Maas, Research Scientist, Google Research, Brain Team, Google.
4. TBA

 

 

 

 

 

 

University of California, Irvine

(UCI)

 

 

Nader Bagherzadeh, Professor (Joint Appointment), Electrical Engineering and Computer Science & Donald Bren School of Information and Computer Science.
 

Panelist.  

 

 

Bio: Dr. Nader Bagherzadeh has been involved in research and development in the areas of computer architecture, reconfigurable computing, VLSI chip design, and computer graphics. For almost ten years ago, he was the first researcher working on the VLSI design of a Very Long Instruction Word (VLIW) processor. Since then, he has been working on multithreaded superscalars and their application to signal processing and general purpose computing. His current project at UC, Irvine is concerned with the design of coarse grain reconfigurable pixel processors for video applications. The proposed architecture, called MorphoSys, is versatile enough to be used for digital signal processing tasks such as the ones encountered in wireless communications and sonar processing.  DARPA and NSF fund the MorphoSys project (total support $1.5 million). Dr. Bagherzadeh was the Chair of Department of Electrical and Computer Engineering in the Henry Samueli School of Engineering at University of California, Irvine. Before joining UC, Irvine, from 1979 to 1984, he was a member of the technical staff (MTS) at AT&T Bell Laboratories, developing the hardware and software components of the next-generation digital switching systems (#5 ESS). Dr. Bagherzadeh holds a Ph.D. in computer engineering from The University of Texas at Austin. As a Professor, he has published more than a hundred articles in peer-reviewed journals and conference papers in areas such as advanced computer architecture, system software techniques, and high performance algorithms. He has trained hundreds of students who have assumed key positions in software and computer systems design companies in the past twelve years. He has been a Principal Investigator (PI) or Co-PI on more than $2.5 million worth of research grants for developing next-generation computer systems for solving computationally intensive applications related to signal and image processing. 

 

 

 

University of Texas at Austin

 

 

Keynote

 

 

 

 

Lizy Kurian John, Ph.D., P.E. The Cullen Trust for Higher Education Endowed Professor in Engineering No.3, IEEE Fellow, Department of Electrical and Computer Engineering, University of Texas at Austin.
 

 

“Machine Learning for Performance and Power Modeling / Prediction."
 


Abstract:  Estimating the power and thermal characteristics of SoCs is essential for designing its power delivery system, packaging, cooling, and power/thermal management schemes. Power models that estimate the power consumption of each functional unit/hardware component from first principles are slow and tedious to build. Machine learning can be used to create power models that are fast and reasonably accurate. Machine learning can also be used to calibrate analytical models that estimate power. In this talk, I’ll present some examples of performance and power modeling using machine learning. Another application for machine learning has been to create max power stressmarks. Manually developing and tuning so called stressmarks is extremely tedious and time-consuming while requiring an intimate understanding of the processor. In our past research, we created a framework that uses machine learning for the automated generation of stressmarks. In this talk, the methodology of the creation of automatic stressmarks will be explained. Experiments on multiple platforms validating the proposed approach will be described. Yet another application for machine learning is in cross-platform performance and power prediction. If one model is slow to run real-world benchmarks/workloads, is it possible to predict/estimate the performance/power by using runs on another platform? Are there correlations that can be exploited using machine learning to make cross-platform performance and power predictions? A methodology to perform cross-platform performance/power predictions will be presented in this talk.

Bio: Lizy Kurian John is Cullen Trust for Higher Education Endowed Professor in the Electrical and Computer Engineering at the University of Texas at Austin. She received her Ph. D in Computer Engineering from the Pennsylvania State University. Her research interests include workload characterization, performance evaluation, memory systems, reconfigurable architectures, and high performance architectures for emerging workloads. She is recipient of many awards including The Pennsylvania State University Outstanding Engineering Alumnus 2011, the NSF CAREER award, UT Austin Engineering Foundation Faculty Award, Halliburton, Brown and Root Engineering Foundation Young Faculty Award 2001, University of Texas Alumni Association (Texas Exes) Teaching Award 2004, etc. She has coauthored books on Digital Systems Design using VHDL (Cengage Publishers, 2007, 2017), a book on Digital Systems Design using Verilog (Cengage Publishers, 2014) and has edited 4 books including a book on Computer Performance Evaluation and Benchmarking. In the past, she has served as Associate Editor of IEEE Transactions on Computers, IEEE Transactions on VLSI, IEEE Computer Architecture Letters, ACM Transactions on Architecture and Code Optimization, and IEEE Micro. She is currently the Editor-in-Chief of IEEE Micro. She holds 12 US patents and is an IEEE Fellow (Class of 2009).

 

 

 

Afternoon Break

Afternoon Break

 

 

 

 

 

Google

 

 

Keynote

 

 

 

 

Dr. Martin Maas, Research Scientist, Google Research, Brain Team.
 

 

“TBA"

 

Abstract: TBA

 

Bio: Research Scientist in the Google Brain team. Before joining Google, I completed my PhD in the Electrical Engineering and Computer Sciences department at UC Berkeley, working with Krste Asanović and John Kubiatowicz. My primary research interests are in managed language runtime systems, operating systems and computer architecture. I am interested in the entire stack from the hardware to the programming systems layer. At Google Brain, I am working on topics related to machine learning. My PhD research focused on warehouse-scale computers. I worked and collaborated across areas and built real systems that involve large system-level codebases as well as hardware-level RTL. I have applied this approach to domains ranging from security to managed languages. During my PhD, I built a secure processor that provides memory-trace obliviousness (a new security property) and can be targeted by a custom compiler, a distributed language runtime system that coordinates JVMs on different nodes in a cluster, and worked on hardware support for garbage collection. I have also built research infrastructure, including FPGA implementations of hardware based on the RISC-V ISA.  Before coming to UC Berkeley, I completed my undergraduate degree at the University of Cambridge. In my undergraduate research, I investigated the challenges and bottlenecks of implementing a Java Virtual Machine for the Barrelfish Operating System. I was supervised by Ross McIlroy and Tim Harris from Microsoft Research, Cambridge.   During my time in high-school, I was an active participant in science and programming competitions. I was on the German team for the International Olympiad of Informatics (IOI) and represented Germany at the International Science and Engineering Fair (ISEF).

 

 

 

 

 

 

ARM

 

 

 

 

 

 

 

Dr. Rob Aitken, R&D Fellow and technology lead for Arm Research, ARM.
 

 

“How to Feed Your Accelerators – Requirements for Next Generation Memory Systems.”

 

Abstract: TBA

 

Bio:

Rob Aitken is an Arm Fellow and technology lead for Arm Research. He is responsible for technology direction of Arm research, including identifying disruptive technologies, monitoring the global technology landscape, and coordinating research efforts within and outside of Arm. His role includes developing strategic relationships with universities, consortia, and other key participants in the global research community. His research interests include emerging technologies, memory design, design for variability, resilient computing, and statistical design. He has published over 80 technical papers on a wide range of topics including impacts of technology scaling, statistics of memory bit cell variability and the use of static current monitoring as a circuit testing and diagnostic mechanism. He holds over 30 US patents. Dr. Aitken joined Arm as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP. He has given keynote addresses, tutorials and short courses at conferences and universities worldwide. He holds a Ph.D. from McGill University in Canada. Dr. Aitken is an IEEE Fellow, and served as General Chair for the 2019 Design Automation Conference.

 

 

 

 

 

 

IHS Markit Technology

 

 

 

 

 

 

Paul Pickering, Senior Analyst, Industrial Semiconductors, IHS Markit Technology

 

 

“Semiconductor Market.”

 

Abstract: TBA

 

Bio: Paul Pickering has over 35 years of engineering and marketing experience, including stints in automotive electronics, precision analog, power semiconductors, flight simulation and robotics. Originally from the North-East of England, he has lived and worked in Europe, the US, and Japan. He has a B.Sc. (Hons) in Physics & Electronics from Royal Holloway College, University of London, and has done graduate work at Tulsa University. In his spare time, he plays and teaches the guitar in the Phoenix, Ariz. area

 

 

 

Panel

 

 

 

Panel:


“How AI and Machine Learning will Drive the Semiconductors Market to the Next Level."


Moderator: Farhad Mafie, SoC Conference Chairman.

Panelists:

1. Anil Mankar, COO & SVP Engineering, BrainChip Inc.
2. TBA.
3. TBA.
4. TBA.

 

This Panel Is Open To Everyone . . .  Register Online for FREE Panel Pass

 

 

 

Savant Company Inc.

 

 

SoC Conference

 

 

 

 

 

 

 

 

Farhad Mafie, SoC Conference Chairman.

 

 

Moderator

 

Farhad Mafie, President and CEO of Savant Company Inc., has over 25 years of experience in high-tech industries including semiconductor and computer businesses; additionally, he has more than 15 years of university-level teaching experience. A seasoned technical executive with extensive global experience in marketing, sales, and engineering. He enjoys developing business plan and go-to-market strategies for innovative and disruptive technologies, deal making, developing strategic alliances and partnerships.


In 2017, he became the CEO of Handycash Inc., a newly formed startup in Switzerland, developing an innovative mobile payment system based on Blockchain technology that will be launched in May 2020 in Germany.
 

For almost six years at Microsemi Corporation, as Vice President of Worldwide Product Marketing and Corporate Communications teams (in US, EU, India, and China), Farhad developed and managed the entire Microsemi’s worldwide outbound and inbound marketing strategies and programs; and worked directly with executive team on M&A projects and successfully integrating over 22 acquired companies.
 

Farhad is also the former Vice President of Marketing/Business Development and Technical Sales Engineering at Toshiba America Electronic Components, Inc. He was responsible for marketing the entire Toshiba standard ICs products in North America, as well as engineering development for Toshiba's Embedded and Digital Consumer products based on ASSP and SoC models.
 

Farhad has worked at Lucent Technologies on marketing communications ICs, Toshiba Information Systems on product definition for Toshiba's notebooks PCs and handheld products, Unisys on designing new processors and computer systems, Ocean Scientific on designing medical instrumentations, and MSI Data on designing data collection products. He has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton.
 

In 2003, Farhad designed, developed, and launched the annual Internationals System-on-Chip (SoC) Conference, Exhibits, and Workshops http://www.socconference.com. For two exciting days, this annual international Conference brings the most innovative and groundbreaking Chip-related technologies to its targeted audience. As the SoC Conference Chairman, he has driven the Conference leading-edge program at UC Irvine for the past 16 years.
 

In 2019, Blockchain Technology Summit was launched to bring the latest blockchain-related technologies, applications and startups in an exciting and educational Summit for worldwide audience http://www.blockchaintechnologysummit.com.
 

Farhad is an author and a translator. In 2003, he published the biography of Iranian poet and Nobel nominee who lived in exile, Nader Naderpour (1929-2000), Iranian Poet, Thinker, Patriot. Farhad is also Editor-in-Chief for the CRC Press SoC Design and Technologies Book Series, which includes (1) Low-Power NoC for High-Performance SoC Design and (2) Design of Cost-Efficient Interconnect Processing Units.
 

Farhad is a member of two UCI Advisory Committees: Communication System Engineering and Embedded System Engineering Certificate Programs. He is also the chair of IEEE Orange County Solid-State Circuits Society (SSCS), as well as IEEE Orange County Entrepreneurs' Network (OCEN).

 

     

 

BrainChip

 

 

Anil Mankar, COO & SVP Engineering, BrainChip Inc.


 

Panelist.  

 

 

Bio: Anil Mankar has spent 30 years developing products in the semiconductor industry. At Western Digital, Mr. Mankar developed PC core Logic chipsets. During his years at Conexant Systems Inc. in the position of VP of Engineering, he developed multiple products across industry segments and later became the company’s Chief Development Officer overseeing all product development for V92 Modem, DSL, Set-top boxes, PC audio and video ‘System on a Chip’ products. Mr. Mankar was SVP of VLSI Engineering at Mindspeed Technologies, responsible for Wireless and VOIP infrastructure product development.
 

 

 

Tabletop Exhibition

Student Design Contest & Reception

Open to Public

 

Tabletop Exhibition

Student Design Contest & Reception

Open to Public

 

 

   

Day TWO Thursday, October 17, 2019

 

SoC Conference Program Agenda*

 

 

Savant Company Inc.

 

 

SoC Conference

 

Farhad Mafie, SoC Conference Chairman.

 

 

Moderator

 

Farhad Mafie, President and CEO of Savant Company Inc., has over 25 years of experience in high-tech industries including semiconductor and computer businesses; additionally, he has more than 15 years of university-level teaching experience. A seasoned technical executive with extensive global experience in marketing, sales, and engineering. He enjoys developing business plan and go-to-market strategies for innovative and disruptive technologies, deal making, developing strategic alliances and partnerships.


In 2017, he became the CEO of Handycash Inc., a newly formed startup in Switzerland, developing an innovative mobile payment system based on Blockchain technology that will be launched in May 2020 in Germany.
 

For almost six years at Microsemi Corporation, as Vice President of Worldwide Product Marketing and Corporate Communications teams (in US, EU, India, and China), Farhad developed and managed the entire Microsemi’s worldwide outbound and inbound marketing strategies and programs; and worked directly with executive team on M&A projects and successfully integrating over 22 acquired companies.
 

Farhad is also the former Vice President of Marketing/Business Development and Technical Sales Engineering at Toshiba America Electronic Components, Inc. He was responsible for marketing the entire Toshiba standard ICs products in North America, as well as engineering development for Toshiba's Embedded and Digital Consumer products based on ASSP and SoC models.
 

Farhad has worked at Lucent Technologies on marketing communications ICs, Toshiba Information Systems on product definition for Toshiba's notebooks PCs and handheld products, Unisys on designing new processors and computer systems, Ocean Scientific on designing medical instrumentations, and MSI Data on designing data collection products. He has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton.
 

In 2003, Farhad designed, developed, and launched the annual Internationals System-on-Chip (SoC) Conference, Exhibits, and Workshops http://www.socconference.com. For two exciting days, this annual international Conference brings the most innovative and groundbreaking Chip-related technologies to its targeted audience. As the SoC Conference Chairman, he has driven the Conference leading-edge program at UC Irvine for the past 16 years.
 

In 2019, Blockchain Technology Summit was launched to bring the latest blockchain-related technologies, applications and startups in an exciting and educational Summit for worldwide audience http://www.blockchaintechnologysummit.com.
 

Farhad is an author and a translator. In 2003, he published the biography of Iranian poet and Nobel nominee who lived in exile, Nader Naderpour (1929-2000), Iranian Poet, Thinker, Patriot. Farhad is also Editor-in-Chief for the CRC Press SoC Design and Technologies Book Series, which includes (1) Low-Power NoC for High-Performance SoC Design and (2) Design of Cost-Efficient Interconnect Processing Units.
 

Farhad is a member of two UCI Advisory Committees: Communication System Engineering and Embedded System Engineering Certificate Programs. He is also the chair of IEEE Orange County Solid-State Circuits Society (SSCS), as well as IEEE Orange County Entrepreneurs' Network (OCEN).

 

     

 

Lunch

Lunch

 

 

Nantero, Inc.

 

 

Bill Gervasi, Principal Systems Architect, Nantero, Inc.

 

“Nantero NRAM Redefines Memory.”
 

 

Abstract: A Holy Grail of memory technologies would be a memory cell with the performance of a DRAM but with persistence and unlimited write endurance. Nantero NRAM is such a technology and more, employing electrostatically switched carbon nanotubes to construct a persistent memory cell array with a wide operating temperature range, low power, low cost due to simple manufacturing processes, and perhaps best of all, NRAM is licensable for incorporation into any design. The focus of this talk is on applications, however, exploring how assembling persistent memory into crosspoints for mass storage or transistor-per-element arrays for local storage changes how system designers can approach a wide variety of applications ranging from AI and deep learning to storage subsystems to non-von Neumann architectures.

Bio: Mr. Gervasi has over 40 years of experience in high speed memory subsystem definition, design, and product development. Career highlights include 19 years at Intel where he was systems hardware designer, software designer, and strategic accounts manager. Mr. Gervasi subsequently was with S3 where he was a graphics architecture specialist and at Transmeta as memory technology analyst. Most recently he held several key positions with companies such as Netlist, SimpleTech, and US Modular driving unique memory module configurations. He is now Principal Systems Architect for Nantero, developing non-volatile RAM-class memories. Mr. Gervasi been involved in the definition of Double Data Rate SDRAM since its earliest inception. He has served on the JEDEC Board of Directors and chaired committees for DRAM parametrics and small form factor memory modules during the development of DDR1 through DDR5. He is currently the chairman of the JEDEC Non-Volatile Memory committee.
 

 

 

Mellanox Technologies Inc.

 

 

 

 

Reuven Badash - Director of Product Marketing, Mellanox Technologies Inc.
 

 

“SmartNIC SoC: What is it and why would I need one?”
 

 

Abstract: Something interesting is going on lately in the networking industry where we start to see SoC components moving from the server towards the network. Instead of using regular NIC, companies start moving to use SmartNIC where a main SoC is installed on the network card. The SmartNIC introduce a new aspect of having compute resource with dedicated hardware-based offloads at the network edge enables to run more tasks in higher performance and free up the main host CPU. At the same time, SmartNIC can take over security related tasks like, encryption and decryption as well as security rules deployment in the data center. In this section, we would show the advantage of SmartNIC and its capabilities to enable better business model of customers.

Bio: Reuven is a director of product marketing in Mellanox technologies inc. At Mellanox he leads the product and marketing activities of BlueField SoC which is the first SoC of the company used for Storage and SmartNIC products. Prior to Mellanox, he served as Head of advanced R&D lab at Samsung leading state of the art technology research and projects. Reuven has more than 20 years of experience in the semiconductor industry as a senior management position.
 

 

 

University of Michigan

 

 

 

 

Dr. Afzaal Qamar, Postdoctoral Research Fellow, EECS, University of Michigan.
 

 

“III-V on Silicon Electro-acoustic Devices and Systems.”
 

 

Abstract: TBA


Bio: TBA.
 

 

 

UCSD 

 

 

Tajana Simunic Rosing, Full Professor & Fratamico Endowed Chair, Dept of CSE and ECE, IEEE Fellow, Director of System Energy Efficiency Lab at UCSD.  


 

“Hyperdimensional Computing and Applications"

Abstract: TBA

 

Bio: Tajana Simunic Rosing is a Professor, a holder of the Fratamico Endowed Chair, IEEE Fellow, and a director of System Energy Efficiency Lab at UCSD. Her research interests are in energy efficient computing, cyber-physical and distributed systems. She is leading a number of projects, including efforts funded by DARPA/SRC JUMP CRISP program, with focus on design of accelerators for analysis of big data, a project focused on developing AI systems in support of healthy living, SRC funded project on IoT system reliability and maintainability, and NSF funded project on design and calibration of air-quality sensors and others. She recently headed the effort on SmartCities that was a part of DARPA and industry funded TerraSwarm center. Tajana led the energy efficient datacenters theme in MuSyC center, and a number of large projects funded by both industry and government focused on power and thermal management. Tajana’s work on proactive thermal management and ambient-driven thermal modeling was instrumental in laying the groundwork in this field, and has since resulted in a number of industrial implementations of these ideas. Her research on event driven dynamic power management laid the mathematical foundations for the engineering problem, devised a globally optimal solution and more importantly defined the framework for future researchers to approach these kinds of problems in embedded system design. From 1998 until 2005 she was a full time research scientist at HP Labs while also leading research efforts at Stanford University. She finished her PhD in EE in 2001 at Stanford, concurrently with finishing her Masters in Engineering Management. Her PhD topic was dynamic management of power consumption. Prior to pursuing the PhD, she worked as a senior design engineer at Altera Corporation. She has served at a number of Technical Paper Committees, including being an Associate Editor of IEEE Transactions on Mobile Computing, an Associate Editor of IEEE Transactions on Circuits and Systems, and a Guest Editor for the Special Issue of IEEE Transactions on VLSI.
 

 

 

 

 

 

IBM

 

 

Keynote

 

 

 

 

 

Jason S. Miller, Director, IBM Z Processor and Systems Chips Development.
 

 

"The Technology Behind the Latest IBM Z Mainframe"

 

Abstract: Mainframes are the IT foundation of the global economy. Every day, over $25B of credit card and ATM transactions flow through the platform, as well as millions of airline reservations, hotel bookings, car rentals, etc. In this talk, we will look at the custom silicon technology that powers this essential platform, including the ultra high-frequency central processor, the custom I/O data routers, and the industry-leading hardware encryption engines. Included in this talk will be a discussion of the pre-silicon verification methodologies that enable us to bring highly complex processors and SOCs to market in record time.


Bio: Jason Miller is the Director of IBM Z Processor and Systems Chips Design at IBM. He leads a global team responsible for designing and bringing to market the industry-leading high performance processors and SOCs that power IBM Mainframes. Prior to this role, Jason led Procurement Engineering for IBM, supporting all procured hardware components and technologies for IBM Systems. Over his career, Jason has held numerous roles in Systems Hardware Development, ASIC Design, Semiconductor Manufacturing, and Microelectronic Packaging. Jason joined IBM in 2000. He holds a BS in Mechanical Engineering from Penn State University.

 

 

 

Lunch

Lunch

 

 

AONDevices

 

 

Mouna Elkhatib, CEO, AONDevices. 


 

“Ultra-Low Power & Always-on AI Voice and Audio recognition: Challenges and opportunities.”
 

Abstract: The proliferation of ‘always-listening’ voice control technology in battery powered applications is currently limited by the fact that there is no solution available that is at the same time accurate enough to be reliable in a noisy environment, low enough power for always-on battery powered operation and low cost. Artificial intelligence and in particular deep learning are giving promising results in this space but multiple challenges need to be overcome to create winning solutions. The technology needs to support at the minimum Wake-word detection and voice command recognition, and it has to be ultra-Low power for always-listening voice-enabled applications. It has to offer high accuracy in the presence of background noise and reverb. It also has to be tolerant to variabilities within user, between users and environments. Finally, it should be scalable to detect multiple commands concurrently. Innovation in this space has to include data augmentation, advanced Neural Networks and low power HW implementation.

Bio: Mouna Elkhatib, CEO, AONDevices. Mouna has over 18 years of experience in the semiconductor business with a strong track record as an excellent engineer, cross-functional team leader and technical marketing expert. Prior to AONdevIces, she was the system lead and principal chip architect at Qualcomm for a family of audio codec chips with integrated voice activation. Before that, she held the director of VLSI position at Conexant, managing audio SOC architecture and design. She is one of the key developers of Conexant's PC-HD audio codecs, USB audio codecs/DSP and Voice input processor SOCs for smart speakers. Mouna holds an engineering degree from Ecole Nationale Supérieure d'Electricité et de Mécanique (ENSEM), 11 US patents and multiple awards.
 

 

 

 

 

 

Xilinx

 

 

Keynote

 

 

 

 

 

 

Jennifer Wong, Vice President of FPGA Product Development. Xilinx Inc.
 

 

"A Holistic Approach for System Integration and Performance Optimization."

 

Abstract: Rapid scaling with Moore’s Law and the more recent 3DIC development have led to the shrinking of electronic systems over the last several decades. As scaling continues beyond single CMOS device to include heterogeneous devices in 2.5D and 3D stacking, design methodologies need to keep pace to enable complex integration to achieve optimal system performance. This requires a new holistic approach for design optimization of the integrated silicon, package and PCB leading to miniaturized solutions that have superior performance.


Bio: Jennifer Wong is Corporate Vice President of Silicon Integration at Xilinx, where she is responsible for design methodology and chip-level integration, as well as system signal/power integrity, package and printed-circuit board development. She has contributed to over 8 generations of FPGAs and SoCs at Xilinx. Before joining Xilinx, Jennifer was with Advanced Micro Devices developing CPLDs. She received her Master of Science and Bachelor of Science degrees, both in electrical engineering, from the University of California, Berkeley. In addition, Jennifer has published multiple papers and has earned 45 patents.

 

 

 

Stanford University

 

 

 

Yatish Turakhia; PhD Candidate, Stanford University. 


 

“Hardware Acceleration of Genomic Sequence Alignment and Its Applications.”

 

Abstract: The public release of the Gen-Z Core Specification 1.0 allows silicon providers and IP developers to start working on products based on this exciting new interface. Gen-Z is the right way to address the worldwide explosion of data (180ZB annually by 2025) and the need for a high throughput, low-latency, scalable, memory-centric fabric. Gen-Z responds to the rapid rise in the number of extremely fast devices and enables a memory-centric architecture with full composability. It simplifies memory-to-memory transfers and eliminates the need for side channels and DMA, thus avoiding behind-the-curtain operations that are difficult to understand, evaluate, debug, or update. Gen-Z is designed with security as a key tenet and contains embedded access and security rights. Future versions of Gen-Z will meet the needs of emerging applications such as artificial intelligence, cognitive computing, real-time data analysis, the Edge, and autonomous systems.

Bio: Yatish Turakhia is a fifth year PhD candidate at the Electrical Engineering Department of Stanford University. He is co-advised by Professor Bill Dally and Professor Gill Bejerano. His research focuses designing a co-processor for accelerating a wide-range of algorithms involving genomic sequence alignment – from read assembly to remote homology search. He is a recipient of the NVIDIA Graduate Fellowship (2016). His work has received the Best Paper Award at ASPLOS 2018 and appeared as one of IEEE Micro Top Picks 2018.
 

 

 

Afternoon Break

Afternoon Break

 

 

Intrinsic ID

 

 

 

 

 

 

 

Dr. Pim Tuyls, Founder and Chief Executive Officer, Intrinsic ID.

 

 

“Eyes Wide Shut: Is Today's Silicon Secure?”
 

 

Abstract: The Internet of Things growth continues to accelerate and create opportunity. But, as many who are responsible for their companies’ success and survival often seem content to ignore, so does the security risk. Ensuring IoT security has not kept pace with the rapidly evolving threat model. This should prompt many questions for those whose business relies on a secure IoT. “Can we be sure a device’s firmware hasn’t been altered by hackers?” “Is secure two-way communications possible?” “Can we scale to trillions of devices in a way that’s commercially viable?” And “Will the microcontroller I design into my product today actually protect it during its whole lifecycle?” Securing endpoints in a reliable and robust method to achieve trust in the IoT can come at a significant cost. Strong device authentication is pivotal to confidently scale in a profitable manner. In this talk, Intrinsic ID CEO Pim Tuyls will describe how use of unclonable identities for IoT products is the best way to establish strong security in an industrial setting, and do so in an economically viable manner.

Bio: Pim Tuyls is CEO of Intrinsic ID, a company specializing in IoT security technology. Before founding Intrinsic ID in 2008 he was at Philips Research, where he was Principal Scientist and managed the cryptography cluster. While there he initiated the work on Physical Unclonable Functions (PUFs), which forms the basis of Intrinsic ID’s silicon fingerprinting technology. Tuyls has a Ph.D. in mathematical physics from Leuven University, holds more than 50 patents and is widely acknowledged for his work in the field of security for embedded applications.

 

 

 

Indiana Institute of Technology

 

 

Wasim Alim, Associate Professor of Computer Engineering, Indiana Institute of Technology.
 

 

“Use of EMG to Control Lower Limb Prosthesis".
  

 

Abstract: Loss of a limb is a traumatic experience for an amputee. In order to integrate these individuals back into society in a productive way, there is a need to address their psychological wellbeing, as well as, their physiological deficiencies should be addressed where they can function in a normal way. The movement of the limbs is controlled through the skeletal muscles when they are neurologically activated. There is a change in electrical potential in the muscle cells as a result of this neurological activity which can be detected through electromyography techniques using surface electrodes. Electromyography has been mainly used for upper limb prosthetic solutions. A bionic prosthetic solution is proposed for lower limb amputees using electromyography. The mechanical knee joint will be controlled through an onboard microcontroller based embedded system. The raw electrical signals detected by surface electrodes will go through multiple stages of signal processing in order to be used by the microcontroller-based system. The microcontroller will provide real-time feedback response to control the motion of the mechanical components using stepper motors. The future plan for this technology is the integration of the microcontroller and the associated circuitry into a system-on-chip (SoC) solution that would bring further benefits such as significantly lower power consumption, smaller area, lighter weight, and more.


Bio: TBA.

 

 

 

netObjex

 

 

Raghu Bala, CEO, NetObjex.
 

 

“A Real-time Smart Factory Automation System."
  

 

Abstract: LAs Industry 4.0 takes hold, the processes involved in automation and mechanization will evolve in factories globally. The fourth Industrial Revolution is a fusion of technologies that blur the lines between the physical, digital, and biological ecosystems known as cyber-physical systems. Factories would embrace cyber-physical systems in manufacturing in order to optimizes processes. The Smart Factory would leverage: Internet of Things, Robotics, SaaS/Cloud, Knowledge Automation, Drones, and Artificial Intelligence.  IOT will be used to proactively manage processes with a real-time feedback loop. Robotics would help make significant efficiency gains by enabling 24/7 production while improving speed and accuracy, simultaneously lowering costs and improving quality and consistency. SaaS/Cloud will quickly scale infrastructure by reducing costs and enabling manufacturers to stay focused on core competencies instead of IT. Knowledge Automation will contribute by taking an individual’s knowhow and transforming it into organizational intelligence. Drones can play a valuable role in gaining flexibility in the times and locations for pickups and deliveries; helping transportation in situations that are otherwise inconvenient, expensive or dangerous; save money counting inventory. AI can assist in predicting and forming recommendations or conclusions based on complex data about products, processes, the production environment, customer trends and outside factors. We will study how these technologies can come together to create a whole new platform for operating the Smart Factories of the future.
 


Bio: TBA.

 

 

 

Panel

 

"FREE"

Panel:

 
“Is Blockchain of Things IoT 2.0? Could Blockchain of Things be the Security solution that the industry has been looking for?"


 
Moderator: Farhad Mafie, SoC Conference Chairman.

Panelists:


1. Dr. Bhaskar Krishnamachari, Professor of Electrical Engineering & Computer Science; Director of Center for Cyber-Physical Systems and the Internet of Things, USC Viterbi School of Engineering.
2. Dr. Pim Tuyls, Founder and Chief Executive Officer, Intrinsic ID.

 

 This Panel Is Open To Everyone . . .  Register Online for FREE Panel Pass

 

 

 

Savant Company Inc.

 

 

 

 

 

 

 

 

 

 

Farhad Mafie, SoC Conference Chairman.

 

 

Moderator

 

Farhad Mafie, President and CEO of Savant Company Inc., has over 25 years of experience in high-tech industries including semiconductor and computer businesses; additionally, he has more than 15 years of university-level teaching experience. A seasoned technical executive with extensive global experience in marketing, sales, and engineering. He enjoys developing business plan and go-to-market strategies for innovative and disruptive technologies, deal making, developing strategic alliances and partnerships.


In 2017, he became the CEO of Handycash Inc., a newly formed startup in Switzerland, developing an innovative mobile payment system based on Blockchain technology that will be launched in May 2020 in Germany.
 

For almost six years at Microsemi Corporation, as Vice President of Worldwide Product Marketing and Corporate Communications teams (in US, EU, India, and China), Farhad developed and managed the entire Microsemi’s worldwide outbound and inbound marketing strategies and programs; and worked directly with executive team on M&A projects and successfully integrating over 22 acquired companies.
 

Farhad is also the former Vice President of Marketing/Business Development and Technical Sales Engineering at Toshiba America Electronic Components, Inc. He was responsible for marketing the entire Toshiba standard ICs products in North America, as well as engineering development for Toshiba's Embedded and Digital Consumer products based on ASSP and SoC models.
 

Farhad has worked at Lucent Technologies on marketing communications ICs, Toshiba Information Systems on product definition for Toshiba's notebooks PCs and handheld products, Unisys on designing new processors and computer systems, Ocean Scientific on designing medical instrumentations, and MSI Data on designing data collection products. He has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton.
 

In 2003, Farhad designed, developed, and launched the annual Internationals System-on-Chip (SoC) Conference, Exhibits, and Workshops http://www.socconference.com. For two exciting days, this annual international Conference brings the most innovative and groundbreaking Chip-related technologies to its targeted audience. As the SoC Conference Chairman, he has driven the Conference leading-edge program at UC Irvine for the past 16 years.
 

In 2019, Blockchain Technology Summit was launched to bring the latest blockchain-related technologies, applications and startups in an exciting and educational Summit for worldwide audience http://www.blockchaintechnologysummit.com.
 

Farhad is an author and a translator. In 2003, he published the biography of Iranian poet and Nobel nominee who lived in exile, Nader Naderpour (1929-2000), Iranian Poet, Thinker, Patriot. Farhad is also Editor-in-Chief for the CRC Press SoC Design and Technologies Book Series, which includes (1) Low-Power NoC for High-Performance SoC Design and (2) Design of Cost-Efficient Interconnect Processing Units.
 

Farhad is a member of two UCI Advisory Committees: Communication System Engineering and Embedded System Engineering Certificate Programs. He is also the chair of IEEE Orange County Solid-State Circuits Society (SSCS), as well as IEEE Orange County Entrepreneurs' Network (OCEN).

 

     

 

 

USC

 

 

Panelist

 

 

 

Dr. Bhaskar Krishnamachari, Professor of Electrical Engineering & Computer Science; Director of Center for Cyber-Physical Systems and the Internet of Things, USC Viterbi School of Engineering.

 

Panelist
 

Bio:   TBA.

 

 

 

PBV

 

 

Panelist

 

 

 

Stephan Wullschleger, CTO, PBV Kaufmann.

 

Panelist
 

Bio:   TBA.

 

 

 

 

Open To Everyone

 

Reception &  Networking

 

 

 

 

 

 

17th International SoC Conference Closed.

 

 

 

 

 

 

 

* * * * * * *

 

* SoC Conference Program is subject to change.  Savant Company Inc, SoC Conference Organizing Committee, and Technical Advisory Board, reserve the rights to revise or modify the SoC Conference agenda at its sole discretion.

 

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