9th International SoC Conference


	Schedule & Program Summary
SoC Conference Day 1	Wednesday, November 2, 2011 Pacific Ballroom 4 & 5	8:00 am - 5:30 pm
SoC Conference Day 2	Thursday, November 3, 2011 Pacific Ballroom 4 & 5	8:00 am - 7:00 pm
SoC Tabletop Exhibit & Reception	Wednesday, November 2, 2011 Pacific Ballrooms 1, 2, and 3	3:00 pm - 8:00 pm
SoC Workshops	Check the Individual Workshop Schedules
IEEE-OC Tech Job Fair	Wednesday, November 2, 2011 Palm Court & Palm Garden	3:00 pm - 6:00 pm
IEEE-OC Student Design Contest	Wednesday, November 2, 2011	6:00 pm - 7:30 pm

Day One Nov. 2, 2011 - SoC Conference Program Agenda*


Day One Wednesday November 2	Session	Company or University
7:00 am – 6:00 pm	Registration Open All Day Several Opportunities to Win various Prizes Throughout the Conference Program . . . Don't Miss Out!
8:00 - 8:10	"Welcome, Opening Remarks, and Conference Updates." Farhad Mafie, SoC Conference Chairman, Savant Company Inc., President and CEO, IEEE OC SSCS & OCEN Chairs.	Savant Company Inc.
	SOI vs. CMOS for Analog & Digital Circuits – Technology, Trends, Challenges, and Emerging Applications. Track Chairman: Dr. Nader Bagherzadeh, Professor Electrical & Computer Engineering, UC Irvine.
8:10 - 8:40	“SOI technologies at X-FAB and their application space.” Paul Poenisch and Sebastian Schmidt.	X-FAB
8:40 – 9:10	“Compact SPICE Models for Next Generation Transistor Technology.” Dr. Sriramkumar Venugopalan, UC Berkeley, BSIM Group.	UC Berkeley
9:10 – 9:40	“Comparing SOI and Bulk Fully Depleted Devices such as FinFET and Planar CMOS.” Horacio Mendez, Executive Director. Gorden Starkey, IBM.	IBM SOI Industry Consortium
9:40 – 10:10	“Status of Fully Depleted (FD) SOI Technology and Prospect of New Super Steep Cut Off FETs for Ultra Low Power and Harsh Applications.” Professor Jiro Ida, Kanazawa Institute of Technology, Japan.	Kanazawa Institute of Technology
10:10 - 10:20	Morning Break
10:20 – 11:00 Keynote	Keynote: “A New Paradigm: Disruptive SoC Design & Market Strategies.” Paul Pickle, Senior Vice President, Integrated Circuit Group.	Microsemi
11:00 - 12:00 Panel	Panel: "3D: Where are we today; Where are we going; and How will you get there with us? Moderator: Steve Leibson, EDA360 Evangelist. Panelists: 1. Herb Reiter, President of EDA 2 ASIC, 3D consultant to GSA. 2. Samta Bansal, Product Marketing, Applied Silicon Realization, Cadence. 3. Dr. Steve Trimberger, Fellow, Circuits & Architectures Group, Xilinx. 4. Paul Hollingsworth, VP of Strategic Marketing, eSilicon. 5. Dr. Jingyi Zhang, Broadcom. 6. Zvi Or-Bach, President & CEO, MonolithIC 3D™ Inc.	Xilinx EDA2ASIC EDA360 Cadence Design Systems Broadcom eSilicon MonolithIC 3D
12:00 pm - 1:00 pm	Lunch
1:00 - 2:00 Panel	Panel: “Emerging Technologies, Trends, and Possibilities in Designing Multicore SoC Platforms." Moderator: Janice Ozguc, Technology Market Analyst, Semiconductor Components and IP, Savant Company Inc Affiliate. Panelists: 1. Dr. Philip Brisk, Assistant Professor, Department of Computer Science and Engineering, UC Riverside. 2. Simon Butler - CEO Methodics. 3. Dr. Dominik Schmidt, Intel. 4. Kurt Prunty, Director of Sales, Target Compiler Technologies, Inc. 5. Tsu-Chang (TC) Lee, Ph.D., Chief Strategy Officer, Etron Technology, Inc. 6. Hans Bouwmeester, Director of the ARM® Center of Excellence, Open Silicon.	Savant Company Inc. Target Compiler Technologies Intel Etron Technology, Inc. UC Riverside. Methodics Open Silicon
2:00 - 2:40 Keynote	Keynote: “Designing SoC That Speak The Same Language as the Nervous System.” Dr. Ralph Etienne-Cummings, Professor Department of Electrical and Computer Engineering, The Johns Hopkins University.	Johns Hopkins University
2:40 - 3:00	Afternoon Break
3:00 – 3:40 Keynote	Keynote: “FPGA are Looking uP.” Dr. Steve Trimberger, Fellow, Circuits & Architectures Group.	Xilinx
	Analog and Mixed-Signal Design Trends and Challenges for Low-Power Embedded SoC Platforms Track Chairman: Dr. Shu Namiki, National Institute of Advanced Industrial Science and Technology (AIST).
3:40 – 4:10	"Challenges of Optical Network Technologies” Dr. Shu Namiki, National Institute of Advanced Industrial Science and Technology (AIST)	National Institute of Advanced Industrial Science and Technology (AIST)- JAPAN
4:10 – 4:40	"The Technological Progress of MEMS-Based Clock Sources.” Dr. Sudhakar Pamarti, Associate Professor, University of California, Los Angeles.	UCLA
4:40 – 5:10	"Practices for Analog and Mixed-Mode Simulations Friendly Design Flow." Erdem Karaadam, Electronics and Communications Engineer.	Ericsson
3:00 pm - 8:00 pm Exhibit Reception & Job Fair	Conference Tabletop Exhibit & Reception Open (Free Exhibit Pass, Many Door Prizes, etc.) Including IEEE-OC Student Design Contest IEEE Tech Job Fair (Palm Court & Palm Garden)

Day TWO Nov. 3, 2011 - SoC Conference Program Agenda*


Day Two Thursday November 3	Session	Company or University
7:00 am – 7:00 pm	Registration Open All Day Several Opportunities to Win various Prizes Throughout the Conference Program . . . Don't Miss Out!
8:00 - 8:10	"Welcome, Opening Remarks, and Conference Updates." Farhad Mafie, SoC Conference Chairman, Savant Company Inc., President and CEO, IEEE OC SSCS & OCEN Chairs.	Savant Company Inc.
	Emerging Technologies, Trends, and Possibilities in Designing Multicore SoC Platforms. Track Chairman: Professor Tadao Nakamura, Department of Information and Computer Science, Keio University, Japan.
8:10 – 8:40	“Asynchronous Methodology and Architecture - The Future of SoC Design.” Michel Laurence, Executive Chairman, Founder and CEO, Octasic Inc.	Octasic Inc
8:40 – 9:10	“The Value of Integrating 3D Audio Into SoC Designs.” Alan Kraemer, Chief Technology Officer, SRS Labs.	SRS Labs
9:10 – 9:40	“Performance and Efficiency of 3D-Stacked DRAM on Multi-core SoCs.” Sachin Idgunji, Principal Engineer, Research and Development Group at ARM.	ARM
9:40 – 10:10	“Using the Marching Memory concept to avoid the Memory Bottleneck.” Professor Tadao Nakamura, Department of Information and Computer Science, Keio University, Japan.	Keio University Japan
10:10 – 10:20	Morning Break
10:20 – 10:50	“Fault-Tolerance and QoS for Network-on-Chip Based Multicores.” Professor, Nader Bagherzadeh, UCI, EECS.	UCI
10:50 – 11:20	“Customizable SoCs: Two Worlds Collide.” Rich Kapusta, Microsemi, Vice President, Microsemi.	Microsemi
11:20 – 12:00 Keynote	Keynote: “Vision For Robots, Vehicles And Consumer Electronics: How Close Are We?” Eugenio Culurciello Associate Professor of Biomedical Engineering Purdue University.	Purdue University
12:00 – 1:00	Lunch
	Green Chips: Technologies, Tools, and Methodologies in Designing Ultra Low-Power Multicore SoCs. Track Chairman: Dr. Eugenio Culurciello Associate Professor of Biomedical Engineering Purdue University.
1:00 – 1:30	“Fusion APU and Trends/Challenges in Future Processor Design.” Pankaj Singh, Sr. Manager – Design Engineering, AMD.	AMD
1:30 – 2:00	“Challenges and Architecture of a 200-Gigabit Network Processor” Patrick Bisson – VP Product Management, EZchip.	EZchip
2:00 – 2:30	“The Three R’s: Reliability, Redundancy and Reconfiguration.” Professor Melvin A. Breuer, USC.	USC
2:30 – 3:00	“4G SoC Technology Innovation, from 150Mb UL small cell to 100Gb EPC.” YJ Kim is the General Manager of the Infrastructure Processor Group at Cavium Networks.	Cavium Networks
3:00 – 3:10	Afternoon Break
3:10 – 3:40	“Dynamically Heterogeneous Cores Through 3D Resource Pooling” Houman Homayoun, PhD, NSF-CRA Computing Innovation Fellow University of California, San Diego Department of Computer Science and Engineering.	UCSD
3:40 – 4:10	“Greening Multicore – Maximizing Performance/Watt Embedded Multicore Software Development – Lessons from the Trenches.” Dr. David Moloney, CTO, Movidius Ltd.	Movidius Ltd
4:10 – 4:20	Afternoon Break
4:20 – 5:20 Panel "FREE"	Panel: “Technology & Entrepreneurship: Dreams, Realities & Opportunities” Moderator: Farhad Mafie, SoC Conference Chairman, Savant Company Inc., President & CEO, IEEE OC SSCS & OCEN Chairs. Panelists: 1. Bruce Sargeant, Founder, President & CTO, Source Scientific. 2. Jeff Greenberg, CEO, Hiperwall. 3. Eric Tanezaki, Intellectual Property Law Partner, Stetina Brunda Garred & Brucker. 4. Jauher Zaidi, Chairman & CEO, Netvinci Inc. 5. Chris LaPlante, Founder & President, Excalibur Engineering. 6. Peter Heydenrych, Chairman and CEO, Corporate Finance Associates. This Panel Is Open To Everyone . . . Register for FREE Panel Pass More Updates Coming Soon . . . Several Opportunities to Win various Prizes During this Panel Discussion . . . Don't Miss Out!	Panel Savant Company Inc. Netvinci Inc. Source Scientific Stetina Brunda Garred & Brucker. Hiperwall Excalibur Engineering Corporate Finance Associates
5:20 – 6:20	Open To Everyone Reception & Networking	Savant Company Inc.
	9th International SoC Conference Closed.

* Program is subject to change. SoC Conference Organizing Committee, Technical Advisory Board (TAB), and Savant Company Inc. reserves the rights to revise or modify the SoC Conference program (the above program) at its sole discretion.

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Wafer images courtesy of Intel Corporation, Micron Technologies & Altera Corporation.