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The 14th International System-on-Chip (SoC)

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University of California, Irvine (UCI) - Calit2

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9th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

 

November 2 & 3, 2011 Radisson Hotel Newport Beach, California

 

SoC Conference Presenters'

Bios & Abstracts

 

If you have any questions or need more information, please contact:

SoC@SavantCompany.com or 949-851-1714   ―  Thank you!

 

a

* Program is subject to change.  SoC Conference Organizing Committee, Technical Advisory Board (TAB), and Savant Company Inc. reserves the rights to revise or modify the SoC Conference program at its sole discretion.

 

 

 

 

 

   

Day One Nov. 2, 2011

 

SoC Conference Program Agenda*

 

 

Savant Company Inc.

 

Farhad Mafie, SoC Conference Chairman, Savant Company Inc., President & CEO,  IEEE OC SSCS & OCEN Chairs.

 

 

"Welcome and Opening Remarks, Technology/Market Trends."

 

 

Farhad Mafie is President and CEO of Savant Company Inc., a technology marketing company in Irvine, CA. Savant specializes in marketing and sales of semiconductor IC/IP products, SoC/ASIC services and solutions, as well as providing targeted technical- and business-related training seminars and conferences globally. He has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience. He is the former Vice President of Marketing and Engineering at Toshiba Semiconductor. He has also worked in strategic marketing, project and design engineering at Lucent Technologies, Unisys, and MSI Data. Farhad has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton. He is an author and a translator, and his articles have been published in a variety of journals and Web-based magazines on technology and political affairs. In 2003, he published the biography of Iranian poet and Nobel nominee who lived in exile, Nader Naderpour (1929-2000), Iranian Poet, Thinker, Patriot. Farhad is also Editor-in-Chief for the CRC Press SoC Design and Technologies Book Series, which includes (1) Low-Power NoC for High-Performance SoC Design and (2) Design of Cost-Efficient Interconnect Processing Units. Farhad is an active member of IEEE, and he is the chair of IEEE Orange County Solid-State Circuits Society (SSCS), as well as IEEE Orange County Entrepreneurs' Network (OCEN). He is also a member of two UCI Advisory Committees: Communication System Engineering and Embedded System Engineering Certificate Programs. 

 

     

   

SOI vs. CMOS for Analog & Digital Circuits – Technology, Trends, Challenges, and Emerging Applications.

Track Chairman:  Dr. Nader Bagherzadeh, Professor Electrical & Computer Engineering, UC Irvine.

 

 

 

X-Fab

 

Paul Poenisch and Sebastian Schmidt. X-FAB.


 

SOI technologies at X-FAB and their application space.

 

Abstract: X-FAB has a long history in providing SIO technologies. The earliest SOI technologies have 1µm minimum feature size. They are, however, quite different in process feature and voltage range. As examples may serve the XD10, enabling a voltage range up to about 700V, which isolation is achieved through deep trenches. The etching technology for these trenches has enhanced over the years and nowadays provides a significant contribution to the MEMS technologies of X-FAB. Trench isolation is also used by the XT06 with 0.6µm minimum feature size, bearing medium voltage (60V) devices, and the XT018 with 0.18µm minimum feature size, providing up to 200V and low voltage devices at around 20V. Of course both all technologies have digital devices with the standard voltages of their size class (XD10, XT06: 5V and XT018: 1.8V). All SOI technologies have in common that the potentials of the devices can be freely chosen as they are isolated against the handle wafer. Additionally the high leakage currents to substrate at high temperature, as in diode isolated technologies, are of no concern due to the dielectric isolation. This is the main distinguishing factor to common bulk technologies and enables a very high temperature range. The freedom of potential enables a wide application range, where isolation between different system parts is necessary. Possible applications are driver circuits for IGBT modules, full bridge rectifiers and multi voltage domain systems. For an IGBT driver, with the XD10 process all three high side driver and the threefold low side driver can be located on one chip. The XT06 is widely used in applications serving two or more voltage levels, even below the ground level of the board. The XT018 is serving applications, where large switch arrays are used. Most of these applications are very difficult to achieve with pure CMOS technologies. The presentation will guide listeners through some examples in more detail and explain why an SOI solution is chosen for this particular SoC.
 

Paul Poenisch is an electrical engineer working in the applications group within the marketing department of X-Fab. His research work focused on modeling of photolithograph processes. He has been in the semiconductor industry for over 32 years working on process and device development for about 25 of those years then switching to the process application area. In that role he works with customers to optimize the application of X-Fab processes to their products. X-Fab Semiconductor Foundries, 275 Saratoga Ave., Santa Clara, CA 95051 USA.
 

 

 

UC Berkeley

 

Dr. Sriramkumar Venugopalan, UC Berkeley, BSIM Group.

 

Compact SPICE Models for Next Generation Transistor Technology. 

 

 

Abstract: Intel recently announced that it will use 22nm FinFET technology for CPU production starting late 2011. This is the beginning of a new era in the IC industry using 3D transistors. At this scale, traditional 2D MOSFETs suffer from a host of problems including variability and power dissipation. One of first demonstration of FinFETs and UTB-SOI transistors on silicon was from the Device Group at UC Berkeley. Multi-gate transistor structures and novel devices will continue to evolve and find place in mainstream technologies post 22nm node. Several advanced device structures are attractive and each has a different performance-cost profile. It is likely that more than one multiple gate structure will be brought to production. Compact models for these advanced devices are needed for technology/circuit development. Furthermore, it is more accurate to compare the device/circuit performances of various device structures using a single compact model sharing as many common modules as possible. We have developed BSIM-MG, a versatile production-ready SPICE model that can capture the behavior of FinFETs, Trigate, UTB-SOI, UTBB-SOI, Gate-all-around (vertical and horizontal) transistors in a unified framework. The model is comprehensive in terms of capturing the various physical effects observed in the multi-gate MOSFETs. One cannot measure device characteristics for all geometries (length, fin height and thickness). The model consists of analytical expressions for currents and capacitances derived from a physical formulation of the device which facilitates accurate extrapolation of device characteristics using parameters tuned to a limited sample set. An analytical description as opposed to time consuming numerical simulations leads to rapid circuit prototyping. The model anticipates effects of advanced technology such as edge effects of multi-fin structures which helps avoiding expensive re-design cycles and leads to faster concept-to-market time. The model not only aims to aid producing digital applications in these advanced technologies, but also foresees analog and RF-CMOS applications by capturing higher order non-linearity through accurate description of self-heating, non-quasi-static effects, and noise etc. BSIM-MG is currently undergoing standardization at the Compact Model Council and is already being deployed in various stages at industries.
 

Bio: Sriramkumar received his B.Tech in Electrical Engg. from Indian Institute of Technology, Kanpur, India in 2008 and M.S in Electrical Engg. from University of California, Berkeley in 2009. He is currently a Graduate Student Researcher with the BSIM Group working under the guidance of industry-renowned Prof. Chenming Hu (TSMC Distinguished Professor in Graduate School) at UC Berkeley. He has been involved in the research and development of turn-key SPICE Compact Models for FinFETs, TriGate, Gate-All-Around transistors (BSIM-CMG), UTB-SOI, UTBB-SOI and Independent Multi Gate transistors (BSIM-IMG) and more recently BSIM6 (an RF design relevant update to BSIM4). His interests are in semiconductor device physics and technology-design interaction. He worked as research intern at Texas Instruments (2011), IMEC (2007) and California Institute of Technology, Pasadena (2006). He was a recipient of number of awards including Frank and Lucas Margaret Fellowship (2008-09) and Caltech-Summer Undergraduate Research Fellowship (2006).

 

 

 

IBM

 

SOI Industry Consortium

 

Horacio Mendez, Executive Director, SOI Industry Consortium.

 

Comparing SOI and Bulk Fully Depleted Devices such as FinFET and Planar CMOS.   

 

Abstract: The recent announcement of 3D transistors (FinFETs) in 22nm clearly points out to the technical superiority of Fully Depleted Transistors. The benefits of Fully Depleted Transistors have been recognized for some a long time, and are largely due to a much better sub-threshold slope and short channel effects. Fully Depleted transistors can be achieved through two basic approaches: planar Fully Depleted SOI (FD SOI) transistors or with 3D FinFETs. The technical advantage superiority of FD SOI was demonstrated earlier this year. Using an ARM M0 Cortex , FD SOI showed a frequency improvement of over 50% on a migration from 28nm Bulk (LP) to FD SOI at 0.9 volts. The results are even better more impressive at lower voltages. This presentation will focus on the key role that SOI will play in the formation of 2-dimmentional and 3-dimensional CMOS transistors and the excellent analog capabilities that SOI offers.

Bio: TBA.
 

 

 

Kanazawa Institute of Technology

 

Japan

 

Professor Jiro Ida, Kanazawa Institute of Technology, Japan.

 

Status of Fully Depleted (FD) SOI Technology and Prospect of New Super Steep Cut Off FETs for Ultra Low Power and Harsh Applications.

 

Abstract: Present status of SOI device, including ET (extreme thin)-SOI, 3D-FIN, are reviewed. And, FD-SOI technology which already has been in mass production in Japan is shown and discussed from view point of device and circuit interaction on Ultra Low Power Digital, Analog, and RF applications. The capability of FD-SOI is indicated for expanding Ultra Low power Application. The rad-hard related projects of JAXA’s (Japan Aerospace Exploration Agency) space application and KEK’s (High Energy Accelerator Organization in Japan) SOI pixel detector are also introduced. Finally, the recent topics of the super steep cut off transistors which S-value is over the theoretical limit, aiming for the future usage on the ultra low voltage power supply, are reviewed. And, some data of the steep S-value obtained by floating body effect in SOI transistor, which is one of the impact ionization MOS (I-MOS), are introduced.


Bio: Dr. Ida had leaded Logic process integrations and FD-SOI Technology at OKI Electric Industry Co., Ltd. in Japan. He also had served as a program committee member of Symposium on VLSI Technology, IEEE international SOI Conf. and SOI Subcommittee of CMC (Compact Model Council) , and was a leader, is now an advisory member of Japan PIDS (Process Integration and Device Structure) Group of ITRS(International Technology Roadmap of Semiconductor). He moved to Kanazawa Institute of Technology as a professor in 2009. He has continued R&D on SOI with many partners in Japan and is interested in device and circuit interaction for ultra low power applications.
 

 

 

Morning Break

 

 

 

Microsemi

 

 

Keynote

 

 

Paul Pickle, Senior Vice President, Integrated Circuit Group.


 

Keynote: "A New Paradigm: Disruptive SoC Design & Market Strategies."

 

Paul Pickle, Senior Vice President, Integrated Circuits Group, Microsemi Corporation.  Paul Pickle has more than 15 years of experience in the electronics industry, and currently runs Microsemi’s Integrated Circuit Divisions including the System-on-Chip and Analog Mixed Signal groups. In this role, Paul leverages the company’s significant design and technical resources in order to accelerate innovative new customer solutions and market focused product introductions. He also plays a key role in defining the strategic direction of the Microsemi, which provides highly reliable, high-performance semiconductors for defense and security; aerospace; enterprise and communications; and industrial and alternative energy applications. Since joining the company in 1998, Paul has held positions of increasing responsibility including Corporate Vice President of Field Applications Engineering, and senior positions in both sales and marketing/product development. Paul’s previous positions include Director of Marketing for GMT Microelectronics Corporation, and engineering positions with All American Semiconductor. He holds a Bachelor of Science in Mechanical Engineering degree with an emphasis on electronics and controls from the University of South Florida - College of Engineering in Tampa, Florida.
 

 

  Panel

Panel: 

 

3D: Where are we today; Where are we going; and How will you get there with us?

 

 
  Panel

 

Xilinx

 

EDA2ASIC

 

EDA360

 

Cadence Design Systems

 

Broadcom

 

eSilicon

 

MonolithIC 3D

Steve Leibson, EDA360 Evangelist.  

 

Moderator

 

 

Bio: Steve Leibson literally wrote the books on IP-based SOC design — “Designing SOCs with Configured Cores,” published in 2006 and “Engineering the Complex SOC,” co-authored with Dr. Chris Rowen and published in 2004. Steve has been evangelizing IP-centric SOC design since 2001 through articles, White Papers, books and book chapters, Webinars, videos, invited keynote presentations, conference presentations, and in-booth trade show presentations around the world. He is now the EDA360 Evangelist and Marketing Director at Cadence Design Systems, a leading EDA vendor specializing in system and chip-level design tools, design IP and IP design platforms, and verification IP. Prior to joining Tensilica as Technology Evangelist, he was VP of Content for Reed-Elsevier/Microdesign Resources, managed and ran the Microprocessor Forum, and he has served as editor in chief of the Microprocessor Report newsletter, EDN Magazine, and Embedded Developer’s journal where he set publication vision and mission and managed editorial and production teams of experienced journalists and writer/engineers. He has many years of experience in persuasively communicating with the electronic design community across a broad range of topics and has made a particular study of reaching the extremely elusive design community for the purpose of lead generation through diverse channels including the Internet, blogs, social media, and online video.

  

Panelists:

 

1. Herb Reiter, President of EDA 2 ASIC, 3D consultant to GSA.
2. Samta Bansal, Product Marketing, Applied Silicon Realization, Cadence.
3. Dr. Steve Trimberger, Fellow, Circuits & Architectures Group, Xilinx.
4. Paul Hollingsworth, VP of Strategic Marketing, eSilicon.
5. Dr. Jingyi Zhang works, Broadcom.
6. Zvi Or-Bach, President & CEO, MonolithIC 3D™ Inc.
 

 
  EDA2ASIC

Herb Reiter, President of EDA 2 ASIC, 3D consultant to GSA.

 


Panelist. 

 

Bio:

 

 

 
  Cadence Design Systems

Samta Bansal, Product Marketing, Applied Silicon Realization, Cadence.

 


Panelist. 

 

Bio:

 

 

 
  Xilinx

Dr. Steve Trimberger, Fellow, Circuits & Architectures Group, Xilinx.

 


Panelist. 

 

 

 

Bio: Dr. Steve Trimberger has been employed at Xilinx since 1988. He is currently a Xilinx Fellow heading the Circuits and Architectures Group in Xilinx Research Labs in San Jose, California. He was the technical leader for the XC4000 design automation software, developed a dynamically-reconfigurable multi-context FPGA, led the architecture definition group for the Xilinx XC4000X device families and designed the Xilinx bitstream security functions in the Virtex families of FPGAs. He has served as Design Methods Chair for the Design Automation Conference, Program Chair and General Chair for the ACM/SIGDA FPGA Symposium and on the technical programs of numerous Workshops and Symposia. He has published three books and dozens of papers on design automation and FPGA architectures. He has more than 170 patents in IC design, FPGA and ASIC architecture, CAE and cryptography. His innovations appear today in nearly all commercial FPGA devices. He is a Fellow of the ACM.

 

 
  eSilicon

Paul Hollingsworth, VP of Strategic Marketing, eSilicon.

 


Panelist. 

 

 

 

Bio: Paul Hollingworth is Vice-President of Strategic Marketing at eSilicon. Prior to joining eSilicon, he was VP Sales and Marketing at Tier Logic, a startup developing 3D FPGAs and ASICs. Before this, he was at Altera for 13 years, first managing Marketing for Altera in Europe before moving to the USA in 2004 as Senior Director of the HardCopy ASIC Group. Prior to that, Mr. Hollingworth spent 11 years in the ASIC industry, working for LSI Logic in England and Germany in technical and marketing roles, and at Thesys (now X-Fab) where he ran the Communications Group. Mr. Hollingworth received a BSEE in physics and electronics and a Masters in microelectronics and management from Durham University in England.

 

 

 
  Broadcom

Dr. Jingyi Zhang, Broadcom.

 

 


Panelist. 

 

 

 

Bio: Dr. Jingyi Zhang received the Ph.D. degree in Electrical Engineering from the State University of New York at Binghamton, NY, in 2010, and is currently working as a staff scientist in infrastructure and networking department in Broadcom Corp.

 

 
  MonolithIC 3D

 

Zvi Or-Bach, President & CEO, MonolithIC 3D™ Inc. 

 


Panelist. 

 

Bio: Zvi Or-Bach is the founder of MonolithIC 3D™ Inc., a Finalist of the “Best of Semicon West 2011” for its monolithic 3D-IC breakthrough. Or-Bach was also a finalist of the EE Times 2011 Innovator of the Year Award for his pioneering work on the monolithic 3D-IC.  Or-Bach has a history of innovative development in fast-turn ASICs for over 20 years. His vision led to the invention of the first Structured ASIC architecture, the first single via programmable array, and the first laser-based system for one-day Gate Array customization. In 2005, Or-Bach won the EETimes Innovator of the Year Award and was selected by EE Times to be part of the "Disruptors" --"The People, Products and Technologies That Are Changing The Way We Live, Work and Play". Prior to MonolithIC 3D, Or-Bach founded eASIC in 1999 and served as the company's CEO for six years. eASIC was funded by leading investors Vinod Khosla and KPCB in three successive rounds. Under Or-Bach's leadership, eASIC won the prestigious EE Times' 2005 ACE Award for Ultimate Product of the year in the Logic and Programmable Logic category. Even before his entrepreneurial ventures in ASIC technology, Or-Bach held engineering management positions at Elbit Computers, Ltd., Israel (subsidiary of Elron) and Honeywell (Lexington, Massachusetts). Zvi Or-Bach received his B.Sc. degree (1975) cum laude in Electrical Engineering from the Technion - Israel Institute of Technology, and M.Sc. (1979) with distinction in Computer Science, from the Weizmann Institute, Israel. He holds over 50 patents, primarily in the field of semi-custom chip architectures.

 
  Lunch

Lunch

 
   

Panel:

 

Emerging Technologies, Trends, and Possibilities in Designing Multicore SoC Platforms. "

 

 

 

Panel

Savant Company Inc.

 

Etron Technology, Inc.

 

Target Compiler Technologies

 

Intel

 

UC Riverside.
 

Methodics

 

Open Silicon

 

Janice Ozguc, Technology Market Analyst, Semiconductor Components and IP, Savant Company Inc Affiliate.    

 

Moderator

 

 

Bio: Janice Ozguc is a technology market analysis concentrating primarily on the semiconductor and IP industries. She has over 25 years of experience in the high tech industry, principally in the areas of executive management, strategic marketing, and business development, as well as design engineering and applications engineering. Prior to establishing her consulting business, Janice was the VP of Business Development for Octalica, a start up developing digital media home networking semiconductors. Her involvement in leading Octalica as part of the four person executive team culminated in a successful acquisition by Broadcom. She has also held executive marketing and sales positions within Entropic, another leader in the home networking space as well as various semiconductor companies including Kawasaki LSI, U.S.A., IBM Microelectronics and Toshiba America. In addition to working with Savant, Janice consults for major financial firms, standards bodies as well as semiconductor and start-up companies. Janice holds an MSEE and undergraduate degrees from Boston University.



Panelists:

 

1. Dr. Philip Brisk, Assistant Professor, Department of Computer Science and Engineering, UC Riverside.
2. Simon Butler - CEO Methodics.
3. Dr. Dominik Schmidt, Intel.
4. Kurt Prunty, Director of Sales, Target Compiler Technologies, Inc.

5. Tsu-Chang (TC) Lee, Ph.D., Chief Strategy Officer, Etron Technology, Inc.

6. Hans Bouwmeester, Open Silicon.

 

 

 

UC Riverside

 

Dr. Philip Brisk, Assistant Professor, Department of Computer Science and Engineering, UC Riverside.

 


Panelist. 

 

 

Bio: Philip Brisk received his B.S., M.S., and Ph.D. degrees, all in Computer Science, from UCLA in 2002, 2003, and 2006 respectively. From 2006-2009, he was a postdoctoral scholar in the Processor Architecture Laboratory at the Ecole Polytechnique Federale de Lausanne (EPFL) in Switzerland. Since 2009, he has been an Assistant Professor in the Department of Computer Science and Engineering at the University of California, Riverside.

Dr. Brisk's research interests include embedded processor architecture and customization, FPGAs and reconfigurable computing, compilers, VLSI-CAD, computer arithmetic, and emerging microfluidic technologies. He has received best paper awards at CASES 2007 and FPL 2009, and has been nominated for best paper awards at DAC 2007 and HiPEAC 2010. He is a member of the ACM and IEEE.
 

 

 

Methodics

 

Simon Butler - CEO, Methodics.


 

Panelist. 
 

 

 

 

Bio: Simon Butler is a graduate of the University of Manchester (UMIST) and has 20 years of engineering experience with IC's. His design/EDA background includes DSP/FFT processor core development, 64bit MIPS processor development, x86 methododology consultant, physical floorplanning EDA tools, mixed signal/analog layout EDA tools. He held various technical lead and engineering management positions at High Level Design Systems (acquired by Cadence), Sandcraft, Cadence, Sabio Labs (acquired by Magma), founded IC Methods LLC in 2000 and co-founded Methodics in 2006.


 

 

 

Intel

 

Dr. Dominik Schmidt, Intel.

 


Panelist. 

 

 

Bio: Dominik Schmidt, M.S.M., Ph.D., PE, has been working in the semiconductor industry for 20 years. He was at Altera working on reconfigurable logic and has worked with Sharp, TI, Cypress, and TSMC. He cofounded Pixel Devices International (PDI) in 1997, one of the first companies to offer CMOS imaging chips. After PDI was acquired by Agilent, he founded Airify Communications, specializing in multi-protocol wireless chip design. After the acquisition of Airify, Schmidt is now at Intel Corporation leading efforts to design the next generation of advanced wireless products. He has also worked for the Stanford Linear Accelerator and Lawrence Berkeley National Laboratory on several advanced projects, and has consulted for several large companies and startups in the mixed-signal and RF design areas. He has taught at UC Extension since 2000 and also teaches at Tsinghua University in Beijing. He is writing a graduate textbook on RF Design for Elsevier Press.

 

 

 

Target Compiler Technologies, Inc.

 

Kurt Prunty, Director of Sales, Target Compiler Technologies, Inc.


 

Panelist. 
 

 

 

Bio: TBA.

 

 

 

 

 

Etron Technology, Inc.

 

Tsu-Chang (TC) Lee, Ph.D., Chief Strategy Officer, Etron Technology, Inc.

 

 


Panelist. 

 

 

Bio: Dr. Tsu-Chang Lee received Ph.D. in Electrical Engineering from Stanford University. The title of his Ph.D. thesis is “Structure Level Adaptation for Artificial Neural Networks”. As a business professional and entrepreneur, Dr. Lee has abundant and diversified technology / product / market / organization development experiences in large, small, and start-up companies. He is currently serving as Chief Strategy Officer for Etron Technology, Inc., a fabless semiconductor company providing memory and I/O IC solutions. He was the founder and CEO for NeoParadigm Labs, Inc.(NPL), a fabless semiconductor company pioneering in providing many “Interconnected Multimedia” SoCs including controllers for LCD displays, networking, and video communications applications. He was Chief Technical Officer for Silvar-Lisco (also called Silicon Valley Research -SVR), one of the earliest pioneers in providing EDA S/W tools. He was manager for Structure IC Design group of Cadence Design Systems.  Being a passionate technology business architect, Dr. Lee is always seeking opportunities to serve and deliver positive influences into the world.  He has also served in many non-profit organizations. Dr. Lee is currently serving as a Leadership Council Member for the American Cancer Society - California Chinese Unit, in which he pioneered the first Relay For Life “in the Cloud” event in 2010, to connect and share with Chinese communities worldwide.
 

 

 

Open Silicon

 

 

Hans Bouwmeester, Director of the ARM® Center of Excellence, Open Silicon.

 

 


Panelist. 

 

Bio: Hans Bouwmeester is director of the ARM® Center of Excellence and director of IP for Open-Silicon and is responsible for IP vendor and core qualification, customer IP selection, and IP integration. Prior to joining Open-Silicon in January of 2007, he spent 14 years with Philips Semiconductors in a variety of initial roles including processor development and IP program management. In 2005 he led a Philips effort to develop reusable IP building blocks for SoC design. In mid 2005 he became director of the Eindhoven IC design center responsible for development of a wide range of products. He has an MSEE degree from Technische Universiteit Delft.

 

 

  Keynote

Dr. Ralph Etienne-Cummings, Professor Department of Electrical and Computer Engineering. Johns Hopkins University.

 

 

Keynote: “Designing SoC That Speak The Same Language as the Nervous System."

 

Abstract: Key barriers to permanent adoption and continuous use of prosthetic devices are their limited functionality and incompatibility with natural human actions. E.g., standard upper limb prosthetics require retraining of remaining muscles, or abnormal contortion of remaining parts of the limb to open/close non-anthropomorphic manipulators. In 2005 a program was initiated by the US Government to develop an upper limb prosthetic device that would be neurally integrated to the body. That is, the prosthetic limb would decode the intent of the user via motor cortex neural recordings, and feedback sensation by somatosenory cortex stimulation. The lofty goal was to develop prosthetic arms that were indistinguishable from “native” ones. As can be expected, despite the quantum leaps of innovation resulting from the program, the ultimate goal of the project remains to be achieved. There are many reasons for the elusiveness of the goal, among them is the need to develop electronics that interface seamlessly with the nervous system, and communicate with it in the same “spike-based” and “neural encoding” language. In this talk, I will describe progress on this front, and project forward to prosthetic devices that will indeed act and feel like native ones. In the future, Luke Skywalker’s arm in Star Wars: The Empire Strikes Back, or extendable memory devices as in Johny Mnumonic will become reality due to developments in neuromorphic engineering.

Bio: Ralph Etienne-Cummings received his B. Sc. in physics, 1988, from Lincoln University, Pennsylvania. He completed his M.S.E.E. and Ph.D. in electrical engineering at the University of Pennsylvania in December 1991 and 1994, respectively. Currently, Dr. Etienne-Cummings is a professor of electrical and computer engineering, and computer science at Johns Hopkins University (JHU). He is the former Director of Computer Engineering at JHU and the Institute of Neuromorphic Engineering (currently administered by University of Maryland, College Park). He was also the Associate Director for Education and Outreach of the National Science Foundation (NSF) sponsored Engineering Research Centers on Computer Integrated Surgical Systems and Technology at JHU. He has served as Chairman of the IEEE Circuits and Systems (CAS) Technical Committee on Sensory Systems and on Neural Systems and Application, and was elected as a member of CAS Board of Governors from 1/2007 – 1/2009. He was also the General Chair of the IEEE BioCAS Conference in 2008, and serves on its Steering Committee. He was also a member of Imagers, MEMS, Medical and Displays Technical Committee of the ISSCC Conference from 1999 – 2006. He also serves on numerous editorial boards and was recently appointed Deputy Editor in Chief for the IEEE Transactions on Biomedical Circuits and Systems. He is the recipient of the NSF’s Career and Office of Naval Research Young Investigator Program Awards. In 2006, he was named a Visiting African Fellow and a Fulbright Fellowship Grantee for his sabbatical at University of Cape Town, South Africa. He was invited to be a lecturer at the National Academies of Science Kavli Frontiers Program, held in November 2007. He won the 2010 JHU Applied Physics Lab R.W. Hart Prize for Best R&D Project in Development. He has also won publication awards, including the 2011 Best Paper Award for IEEE Transactions of Biomedical Circuits and Systems, 2003 Best Paper Award of the EURASIP Journal of Applied Signal Processing and “Best Ph.D. in a Nutshell” at the IEEE BioCAS 2008 Conference, and has been recognized for his activities in promoting the participation of women and minorities in science, technology, engineering and mathematics. His research interest includes mixed signal VLSI systems, computational sensors, computer vision, neuromorphic engineering, smart structures, mobile robotics, legged locomotion and neuroprosthetic devices. He has published ~200 technical articles, 1 book, 9 book chapters and holds 5 patents (plus 2 pending) on his work in these subjects.

 

 

 

Afternoon Break

 

 

   

Analog and Mixed-Signal Design Trends and Challenges for Low-Power Embedded SoC Platforms

Track Chairman:  Dr. Ivo Bolsens, CTO, Senior VP, Xilinx.

 

 
  Keynote

 

Dr. Steve Trimberger, Fellow, Circuits & Architectures Group, Xilinx.

 


Keynote:   “FPGA are Looking uP.”

 

 

 

Bio: Dr. Steve Trimberger has been employed at Xilinx since 1988. He is currently a Xilinx Fellow heading the Circuits and Architectures Group in Xilinx Research Labs in San Jose, California. He was the technical leader for the XC4000 design automation software, developed a dynamically-reconfigurable multi-context FPGA, led the architecture definition group for the Xilinx XC4000X device families and designed the Xilinx bitstream security functions in the Virtex families of FPGAs. He has served as Design Methods Chair for the Design Automation Conference, Program Chair and General Chair for the ACM/SIGDA FPGA Symposium and on the technical programs of numerous Workshops and Symposia. He has published three books and dozens of papers on design automation and FPGA architectures. He has more than 170 patents in IC design, FPGA and ASIC architecture, CAE and cryptography. His innovations appear today in nearly all commercial FPGA devices. He is a Fellow of the ACM.

 

 
   

Analog and Mixed-Signal Design Trends and Challenges for Low-Power Embedded SoC Platforms

Track Chairman:  Dr. Steve Trimberger, Fellow, Circuits & Architectures Group, Xilinx.

 

 

 

National Institute of Advanced Industrial Science and Technology (AIST)

 

Dr. Shu Namiki, National Institute of Advanced Industrial Science and Technology (AIST)

 

Challenges of Optical Network Technologies.
 

 

 

Abstract: It is without doubt that the Internet traffic growth nowadays is inseparable from the economic growth. It is then of general importance for our lives to sustain the traffic growth for future. On the other hand, the current network technologies are facing many fundamental limits from physical to transport layer: the so-called nonlinear Shannon limit; fiber Rayleigh scattering loss limit; quantum limit of optical amplifiers; electronic devices linewidth limits; thermal noise limit; TCP bottleneck etc.. And recently, the energy bottleneck of IP routers is looming due to the rapid penetration of the broadband access to the Internet. This talk will point out that optical technologies are the key for sustainable growth of traffic overcoming the fundamental bottlenecks, while the challenges have yet to be addressed. The 'dynamic optical path network' technologies, recently promoted by authors' group, are expected to enable the capacity of the network to ever scale without an energy crunch, circumventing the fundamental limits mentioned above. As we look at the ingredients of the traffic, the video related contents are the main driver of the traffic growth, which would be better served through path provisioning rather than packet processing. Then, the appropriateness of the optical path switching in conjunction with space-division multiplexing is discussed in this context. Discussions will follow to clarify the key enabling technologies for the proposed dynamic optical path network, and with these technologies given, we will argue that the total energy consumption could be so low as to avoid the energy crunch despite allowing sustainable traffic growth.

 

Bio: Shu Namiki (M’03) received M. S., and Dr. Sci. in physics and applied physics from Waseda University, in 1988 and 1998, respectively. He worked for Furukawa Electric Co., Ltd. from 1988 to 2005, where he developed award-winning high-power pump laser packaging technologies and next generation devices for optical networks such as ultrashort optical pulse sources, multi-wavelength-pumped fiber Raman amplifiers, high performance EDFAs, and nonlinear fiberoptic devices. He also was a visiting scientist at the Massachusetts Institute of Technology, from 1994 to 1997, where he studied mode-locked fiber lasers. In 2005, he joined the National Institute of Advanced Industrial Science and Technology (AIST). He is currently the Team Leader of Optical Signal Processing Systems Team, Network Photonics Research Center, AIST. He has performed technical committee duties for most of the prominent international conferences, such as OFC, ECOC, OAA, CLEO, OECC, COIN, and so forth. He has also served as Associate Editor for Optics Express and Co-Editor-in-Chief for IEICE Transactions on Communications, and is currently an Advisory Editor for Optics Express. Dr. Namiki has co-authored more than 200 conference presentations, papers, book chapters, articles, and patents. He is an OSA Fellow, and member of IEICE, Japan Society of Applied Physics, and IEEE Photonics Society and Communications Society.

 

 

 

UCLA

 

Dr. Sudhakar Pamarti, Associate Professor, University of California, Los Angeles.

 


The Technological Progress of MEMS-Based Clock Sources.

 

Abstract:  Quartz crystal based resonators and clocks have, for long, been the unchallenged timing solutions for the electronics industry. However, in recent years, MEMS based timing solutions have started offering viable alternatives to quartz at least in a subset of applications, owing to an innovative combination of MEMS and IC technologies. This talk will review some of the key innovations that have led to this growth, and discuss the current capabilities of MEMS based clocks and outstanding technological challenges.

 

Bio:  Sudhakar Pamarti received his Ph.D. degrees in electrical engineering from the University of California at San Diego 2003. Prior to joining UCLA in 2005, he worked with Rambus Inc. developing high speed chip-to-chip electrical communication interfaces.

Research: Dr. Pamarti is interested in wireless and wireline communication system hardware, particularly in mixed signal circuits blocks such as data converters, frequency synthesizers, and clock synchronization and signal equalization circuits.  His group focuses on developing digital signal processing and communication theoretic techniques to improve the performance metrics of error-prone mixed signal circuitry. He emphasizes both the in-silicon verification and the theoretical analysis of such techniques. Typical research employs delta-sigma modulation for data conversion, frequency synthesis and power amplification; or, using CDMA for Gb/s chip-to-chip communication.

 

 

 

Ericsson

 

Erdem Karaadam, Electronics and Communications Engineer.


 

 

Practices for Analog and Mixed-Mode Simulations Friendly Design Flow.


 

Bio: The importance of Analog and Mixed-mode simulations is becoming more widely recognized with the trend towards multi-IP integration on SoC. Conventional design flows need to be updated as the capabilities of the modeling languages and the tool capabilities evolve. The main problems are how to address the SoC needs and fill in the verification gaps. This article will propose a way of working with efficient use of modeling languages and give best practices on the matter.

 

Abstract: Erdem Karaadam is an electronics and communications engineer with more than 10 years of experience and project management skills in the area of Analog/ Mixed-Signal IC design. He has worked with companies like Alcatel Microelectronics, STMicroelectronics and STEricsson. He is recently heading the RF/Analog IP Design Team in Ericsson Microelectronics Design Centre in Istanbul/Turkey. Erdem is holding BSc and MSc degrees in Electronics and Communications Engineering, from Istanbul Technical University and Bosphorus University (Istanbul), respectively.

 

 

   

Day TWO Nov. 3, 2011

 

SoC Conference Program Agenda*

 

 

 

Emerging Technologies, Trends, and Possibilities in Designing Multicore SoC Platforms.

Track Chairman:  Professor Tadao Nakamura, Department of Information and Computer Science, Keio University, Japan.

 

     

 

Savant Company Inc.

Farhad Mafie, SoC Conference Chairman, Savant Company Inc., President & CEO,  IEEE OC SSCS & OCEN Chairs.

 

 

 

Farhad Mafie is President and CEO of Savant Company Inc., a technology marketing company in Irvine, CA. Savant specializes in marketing and sales of semiconductor IC/IP products, SoC/ASIC services and solutions, as well as providing targeted technical- and business-related training seminars and conferences globally. He has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience. He is the former Vice President of Marketing and Engineering at Toshiba Semiconductor. He has also worked in strategic marketing, project and design engineering at Lucent Technologies, Unisys, and MSI Data. Farhad has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton. He is an author and a translator, and his articles have been published in a variety of journals and Web-based magazines on technology and political affairs. In 2003, he published the biography of Iranian poet and Nobel nominee who lived in exile, Nader Naderpour (1929-2000), Iranian Poet, Thinker, Patriot. Farhad is also Editor-in-Chief for the CRC Press SoC Design and Technologies Book Series, which includes (1) Low-Power NoC for High-Performance SoC Design and (2) Design of Cost-Efficient Interconnect Processing Units. Farhad is an active member of IEEE, and he is the chair of IEEE Orange County Solid-State Circuits Society (SSCS), as well as IEEE Orange County Entrepreneurs' Network (OCEN). He is also a member of two UCI Advisory Committees: Communication System Engineering and Embedded System Engineering Certificate Programs.

 

     

 

Octasic Inc.

 

Michel Laurence, Executive Chairman, Founder and CEO, Octasic Inc.

 

Asynchronous Methodology and Architecture - The Future of SoC Design.

 

Abstract:  New performance-demanding applications are on the rise and the trend is almost certain to continue. These applications require significant processing power, which ultimately translates to more power consumption, a challenge that has plagued processor design for over a decade. To date, most processor engineers have had to choose between power and performance when it comes to designing their products. One way to address this core issue is by using a self-timed asynchronous architecture. The general characteristics of asynchronous circuits are extremely appealing and hold the potential to address many of the key issues (power consumption, process variation, EMI, etc.) facing processor designers in ever smaller geometries. While much research has been done over the years in the area of asynchronous circuits, and many attempts have been made to apply them to various processors, the results to date have been commercially disappointing. In general those attempts have suffered from one or more of the following drawbacks:
• the realized performance was equal or less than that of state-of-the-art synchronous design,
• the silicon cost was significantly higher than the realized gains justify,
• the circuits needed unique and new silicon elements requiring characterization for reliability at every new process node, and
• the realized processor required new software skills and tools to fully exploit the advantages.

A new asynchronous architecture has emerged that may hold the key to the next generation of processor design and manufacturing by meeting and even exceeding needs in the areas of power and performance. The key to this new architecture is using proven design techniques in new ways. These techniques include source-synchronous clocking and innovative static timing tools. Using this new asynchronous design methodology, processor designers can achieve a 3:1 improvement in power efficiency over current technologies, while maintaining the current software programming paradigm.  Octasic has applied this asynchronous technology to a homegrown DSP core, labeled Opus. Opus 1, the first generation was commercialized in 2008, and serves in the telecommunications infrastructure market. This year, Opus 2, the 2nd generation DSP core, is being released to market. This device covers application spaces including video transcoding and LTE picocells. This presentation will describe the OCT2224 system on chip. It is composed of 24 Opus2 DSP cores as well as an application processor and associated peripherals. Video and wireless baseband processing benchmarks will be presented that show how this DSP Core delivers 3:1 the performance per watt of any competing DSP core in the same process node.  Following this, the presentation will demonstrate how this asynchronous technology can be applied to almost any general-purpose CPU and deliver the same 3:1 improvement in power efficiency. The example given will be based on an ARM A8 implementation. This technology can therefore be applied to a broad range of processors and applications, ranging from network infrastructure equipment to application processors for mobile devices.

Bio: Michel Laurence, Executive Chairman, Founder and CEO.  Michel Laurence is a founding member of Octasic. Prior to Octasic, he was vice president and general manager of the Network Division of Natural MicroSystems (NMS) in Boston. He joined NMS as a result of its acquisition of InnoMediaLogic (IML) which he had founded in 1996 and led as CEO into a thriving multi-million dollar VoP solutions vendor. Previously, Laurence held various technical management positions in the telecom industry in the US and Canada. He graduated from the Royal Military College of Canada in 1973.

 

 

 

SRS Labs

 

Alan Kraemer, Chief Technology Officer, SRS Labs.

 

 

The Value of Integrating 3D Audio Into SoC Designs.

 

 

 

Abstract:  Over the past year, 3D technologies have taken the CE industry by storm and as a product of all the buzz created, OEMs and ODMs have been rushing to bring mobile phones, tablets, PCs and TVs to market with this technology not only to be a part of the 3D buzz, but so they don’t fall behind the curve. This uprising of interest in 3D technology presents a unique opportunity to SoC designers to develop all-inclusive 3D SoC designs that incorporate both 3D visual processing solutions and 3D audio IP that can then be integrated by OEMs to deliver the full 3D experience on their products.  For this technical session, I would like to discuss the surround sound paradigm shift, 3D audio and how it works, why 3D picture only delivers half of the 3D experience, possible alterations to the SoC architecture to support true multi-dimensional audio, a few of SRS’ DSP Core partnerships and how through the incorporation of SRS 3D audio rendering solutions, SoC platform developers can add value to their design and sell through to more OEMs.
 

Bio: Alan Kraemer has over 25 years experience in sales and engineering. At SRS Labs, Kraemer has served in key technology development, most recently as Chief Technology Officer. Kraemer’s vast audio technology knowledge has helped to establish him as an audio expert throughout the CE industry. He’s been a featured speaker at many trade events including: TI Dev Conf. 2007, DisplaySearch Conf. 2007 (2 events), AES 2006, Beijing Digital TV Conf. 2006, Keynote for TI Developer’s Conf. 2005 (3 countries), CTIA 2004, and many more. Kraemer holds patents for several SRS technologies and is actively involved in the development of new audio and voice solutions for the wireless and surround sound markets.  The Value of Integrating 3D Audio Into SoC Designs.

 

 

 

ARM

 

Sachin Idgunji, Principal Engineer, Research and Development Group at ARM.

 

 

Performance and Efficiency of 3D-Stacked DRAM on Multi-core SoCs.


 


Abstract: Technology scaling has kept up with Moore’s law allowing the ability to double the number of transistors in a given area every two years. At the SoC level , multi-core designs are now the driver in increasing the performance in systems from mobile processors to high performance servers. With the shrinking technology nodes, interconnect delay is a key performance limiter and also results in increased power dissipation from the excessive repeaters that need to be added to minimize the impact of the delay. Compounded with the interconnect effect, IOs have not scaled in accordance and grow at a much lower rate resulting in interfaces that are inefficient. 3D-Integration has been an area of active research to address these limitations and also offers the capability to increase system integration through stacking of heterogeneous technologies such as memory stacking on multi-core SoCs. We present the impact of multi-channel 3D-stacked DRAM on system performance and efficiency (performance/watt) in such stacked systems when compared to planar (2D) systems.
 

Bio: Sachin Idgunji is a Principal Engineer in the Research and Development Group at ARM. He has been with ARM since 2006 and his current area of research is in power efficient multi-core system design and is presently working on projects that investigate the opportunities and challenges of 3D-ICs in multi-core systems on chip (SoC). He has filed and received patents in areas of low power, fault tolerant circuits and systems and has worked on various aspects of low power design and how process variation at advanced nodes impacts SoC design. Sachin received his B.E. in Electronics Engineering in 1990 from Shivaji University in India and has over 20 years of industry experience. Prior to joining ARM he held technical lead roles at Synopsys, IBM, Control Net and PCS-Data General.

 

 

 

Keio University

 

Japan

 

 

Professor Tadao Nakamura, Department of Information and Computer Science, Keio University, Japan.

  

Using the Marching Memory concept to avoid the Memory Bottleneck.

 

Abstract: Marching memory integrates all memory including cache memory and some register files into a single unit to avoid the memory bottleneck. DRAM performance is largely limited by the need to address and access data from the memory location furthest from the external pins. Marching memory uses DRAM based memory cell technology but reorganizes the column and row structure. Marching memory is organized to synchronize memory columns in minimizing the wire length between memory cells and the operational units. A side benefit is lower energy consumption in a smaller packaging format. Marching memory removes the memory bottleneck by designing a memory so that its access time corresponds to the cycle time of the executing processor. The basic idea is to create a memory structure wherein the data is scheduled to arrive at a fixed physical memory port for immediate use by the processor’s functional units. Essentially the data comes to the processor rather than the processor searching randomly for the data.

In its most basic form the Simple Marching memory corresponds to a vector processor whose data is shifted to the processing pins one column after another. The Extended Marching memory introduces modes to enable columns to shift right, left or stay in place. The Complex Marching memory partitions the entire memory array into units of Extended Marching memory whose outputs are bussed to the external chip pins. Through this mechanism the Complex Marching memory achieves a restricted random access.
(based on joint work with Michael Flynn)
 

Bio: Tadao Nakamura received his PhD from Tohoku University in 1972. He was a Full Professor at Tohoku University from 1988-2007, and sent internationally his many PhD graduates to universities and industries. Seventeen graduates of his are full professors at universities including an American university. As for Tohoku University Dr. Nakamura is currently a Professor Emeritus of the university, and especially in Japan he is also a Professor of Keio University. From 1994-97 he stayed at Stanford University as a visiting Full Professor of the Electrical Engineering Department, and today he still stays as a visiting Full Professor at any time if any. In 2007 he was also inducted as a Professorial Fellow at Imperial College London (The University of London), and has been making efforts to open his new research laboratory and environments. His recent research interests are in low-power and high-speed computer architectures especially with Marching Memory invented by him and Professor Michael J. Flynn to avoid the memory bottleneck in computer systems. In 2004 he received The IEEE Computer Society’s Taylor L. Booth Award. He has been Advisory Committee Chair, after the Organizing Committee Chair, of COOL Chips conference series fully sponsored by The IEEE Computer Society. He is an IEEE Fellow.

 

 

  Morning Break Morning Break  

 

UCI

 

Professor, Nader Bagherzadeh, UCI, EECS.
 

Fault-Tolerance and QoS for Network-on-Chip Based Multicores.
 

 

Abstract: In this talk first an overview of our current work on NoC based multicore architectures is presented. Next, our current efforts for incorporating fault-tolerance and QoS onto the current platform is presented. With the potential for using NoC communication for multicores with 100's cores, it is essential to develop techniques that handle faults as well as dealing with different priorities for routing messages.

 

Bio: Dr. Nader Bagherzadeh has been involved in research and development in the areas of computer architecture, reconfigurable computing, VLSI chip design, and computer graphics. For almost ten years ago, he was the first researcher working on the VLSI design of a Very Long Instruction Word (VLIW) processor.   Since then, he has been working on multithreaded superscalars and their application to signal processing and general purpose computing.  His current project at UC, Irvine is concerned with the design of coarse grain reconfigurable pixel processors for video applications.  The proposed architecture, called MorphoSys, is versatile enough to be used for digital signal processing tasks such as the ones encountered in wireless communications and sonar processing.  DARPA and NSF fund the MorphoSys project (total support $1.5 million).  Dr. Bagherzadeh was the Chair of Department of Electrical and Computer Engineering in the Henry Samueli School of Engineering at University of California, Irvine.  Before joining UC, Irvine, from 1979 to 1984, he was a member of the technical staff (MTS) at AT&T Bell Laboratories, developing the hardware and software components of the next-generation digital switching systems (#5 ESS).  Dr. Bagherzadeh holds a Ph.D. in computer engineering from The University of Texas at Austin.  As a Professor, he has published more than a hundred articles in peer-reviewed journals and conference papers in areas such as advanced computer architecture, system software techniques, and high performance algorithms.  He has trained hundreds of students who have assumed key positions in software and computer systems design companies in the past twelve years.  He has been a Principal Investigator (PI) or Co-PI on more than $2.5 million worth of research grants for developing next-generation computer systems for solving computationally intensive applications related to signal and image processing.

 

 

 

Microsemi

 

Rich Kapusta, Microsemi, Vice President, Microsemi.

 


Customizable SoCs: Two Worlds Collide.
 

 

 

 

Abstract: Virtually every embedded system today is implemented using a microcontroller and some amount of custom hardware, whether in discrete or programmable form. This is due to the lack of MCUs with the “perfect” feature, which forces engineers to design around problems with additional components. The introduction of customizable SoCs solves this problem. cSoCs combine MCU technology with FPGA and programmable analog, enabling a hardware / software platform which is infinitely more flexible and substantially more integrated than any discrete solution on the market today. Using a single cSoC, an embedded designer no longer has to compromise. Come learn more about this breakthrough technology.

 

Bio:

 


 

 

 

Keynote

 

Purdue University

 

Eugenio Culurciello Associate Professor of Biomedical Engineering Purdue University.

 

Keynote:  “Vision For Robots, Vehicles And Consumer Electronics: How Close Are We?”

 

Abstract:  We discuss the current state of the art in synthetic vision systems for robotics and consumer applications. We ask and partially answer the following questions: when will vehicles, consumer electronics, robotic helpers and computing equipment perform visual tasks that are now only the prerogative of humans? Where is robotic and artificial vision right now? How close are we to embedded vision system that perform at the level of humans? When will robot help our everyday life? We also present the state of the art hardware systems for embedded vision and discuss their performance in comparison with general purpose computer processors, graphic cards, programmable hardware and systems on a chip. We also present the current state-of-the-art work on neuromorphic hardware models of the mammalian visual system. In particular systems that model retinal pre-processing and the ventral visual pathway, with the goal of categorizing, tracking and maintaining a visual memory of tens of targets. More information can be found here: http://www.neuflow.org/

 

Bio: Eugenio Culurciello (S'97-M'99) received the Ph.D. degree in Electrical and Computer Engineering in 2004 from the Johns Hopkins University, Baltimore, MD. He is an associate professor of the Weldon School of Biomedical Engineering at Purdue University, where he directs the ‘e-Lab’ laboratory. His research interest is in analog and mixed-mode integrated circuits for biomedical instrumentation, synthetic vision, bio-inspired sensory systems and networks, biological sensors, silicon-on-insulator design. Eugenio Culurciello is the recipient of The Presidential Early Career Award for Scientists and Engineers (PECASE) and Young Investigator Program from ONR, the Distinguished Lecturer of the IEEE (CASS), and is the author of the book "Silicon-on-Sapphire Circuits and Systems, Sensor and Biosensor interfaces" published by McGraw Hill in 2009.

 

 

 

Lunch

Lunch

 

 

 

Green Chips: Technologies, Tools, and Methodologies in Designing Ultra Low-Power Multicore SoCs.
Track Chairman:  Dr. Ralph Etienne-Cummings, Professor Department of Electrical and Computer Engineering, The Johns Hopkins University.

 

 

 

AMD

 

 

Pankaj Singh, Sr. Manager – Design Engineering, AMD.

 

 

Fusion APU and Trends/Challenges in Future Processor Design.

 

 

Abstract: In January 2011 AMD introduced world’s first APU and pointed the world towards a new way of computing. This was very much a first step in an architectural journey that is well underway at AMD. In this session the speaker talks about AMD’s innovative Fusion architecture which provides heterogeneous computing with excellent visual experience on Graphics. It combines different processing engines in single-chip to strike a unique balance between the dimensions of performance, power consumption thereby delivering Outstanding performance-per -watt-per-dollar. AMD is working to ease the programmer’s access to this new level of compute horsepower and dramatically expand the processing resources available to modern applications by Open CL. The talk highlights benefits of heterogeneous computing and need for open standard programming language such as OpenCL for general purpose computing on GPU’s. The convergence of mobility, communication and computing has produced multifunctional end applications requiring low power, high performance computing. This talk also presents various challenges faced in next generation microprocessor SOC development and discusses ways to improve the productivity and efficiency of SoC design. To improve productivity and efficiency of SoC’s, various options are discussed such as creating/reusing higher building blocks, building high B.W and scalable interfaces for high throughput, 3D stacking to meet high performance, high density and memory bandwidth requirement.
 

Bio: Pankaj work with AMD as Sr. Manager –Design engineering and is responsible for leading SoC verification activities from India for AMD’s next generation fusion products. Pankaj completed his Bachelors in Electronics from REC [NIT] Bhopal in 1993; Master's in Electrical Engineering from USF, Florida and an MBA from SMU, Dallas. Overall he has 18 years of industry experience of working with startup's and also large US/European MNC's. His past work includes various leadership roles such as IP India Design center Manager, full chip SoC Engineering Manager, Design flow department head with company's such as GDA (acquired by Rambus), Texas Instruments and Infineon Technologies. Besides management experience, Pankaj has also published 15 technical papers in various international conferences and has been a board member of few conference committees.

 

 

 

EZchip

 

Patrick Bisson – VP Product Management, EZchip.

 

Challenges and Architecture of a 200-Gigabit Network Processor

 

Abstract: 

100GE target applications
What are NPUs?
Typical router line card
Main NPU functions: Processing, Traffic Management, OAM
Processing challenges at 200Gbps: Required clock cycles, Required I/O bandwidth, Power
EZchip’s NPU architecture fundamentals
NP-5 is a 200Gbps NPU

 

Bio: Patrick Bisson joined EZchip in November 2002 as Senior Director of Technology. Since then, he has played a key role in securing multiple design wins for EZchip’s products and supporting their deployment in customer applications. Previously, from 1997 to 2002, he served as Director of Software Engineering for Siara Systems and Cerent Corporation. His contribution was instrumental to the acquisitions by Redback Networks and Cisco Systems respectively. For seven years prior, Mr. Bisson held several software engineering and management positions at Alcatel. He holds a M.S. in Computer Science from INSA (Institut National des Sciences Appliquées), Lyon, France.
 

 

 

USC

 

Professor Melvin A. Breuer, USC.

 

 

The Three R’s: Reliability, Redundancy and Reconfiguration.

 

 

Abstract: Due to trends in CMOS scaling and the imminent emergence of new computational fabrics, issues related to process variations, defects and noise have resulted in large variations in yield, performance and capability/capacity associated with the mass production of a given design. In the past, test engineers addressed many of these issues. But now it appears that the problems are so great, and solutions proposed by test engineers so costly, that new paradigms are needed. I will suggest three such approaches in this talk, namely (1) that design engineers focus on yield with the same intensity that they have given to logic minimization, high performance and low power; (2) that redundancy can be effectively used for logic and not be restricted to memories; and (3) adopt the premise that all complex chips are defective, and high yield is obtained via identification via diagnosis of circuitry that is functional, and then reconfigure the circuitry so that a marketable product is realized.

 

Bio: Melvin A. Breuer received his Ph.D. in electrical engineering from the University of California, Berkeley, and is the Charles Lee Powell Professor of Electrical Engineering and Computer Science at the University of Southern California. He was Chairman of the Department of Electrical Engineering-Systems from 1991-1994, and again from 2000-2003. He was Chair of the Faculty of the School of Engineering, USC, for the
1997-98 academic year. His main interests are in the area of computer-aided design of digital systems, design-for-test and built-in self-test, and VLSI circuits. Dr. Breuer is the editor and co-author of Design Automation of Digital Systems: Theory and Techniques, Prentice-Hall; editor of Digital Systems Design Automation: Languages, Simulation and Data Base, Computer Science Press; co-author of Diagnosis and Reliable Design of Digital Systems, Computer Science Press; co-editor of Computer Hardware Description Languages and their Applications, North-Holland; co-editor and contributor to Knowledge Based Systems for Test and Diagnosis, North-Holland; and co-author of Digital System Testing and Testable Design, Computer Science Press 1990 and reprinted in 1995 by the IEEE Press. He has published over 230 technical papers and was formerly the editor-in-chief of the Journal of Design Automation and Fault Tolerant Computing, on the editorial board of the Journal of Electronic Testing, the co-editor of the Journal of Digital Systems, and the Program Chairman of the Fifth International IFIP Conference on Computer Hardware Description Languages and Their Applications. He is a co-author of a paper that received an honorable mention award at the 1997 International Test Conference, a co-author of a paper nominated for the best paper award at the 1998 Design Automation and Test in Europe Conf., a co-author of a paper published in the 1998 International Test Conference that was selected to be in a compendium of significant papers over the last 35 years, and a co-author of the best paper at the 2000 Asian Test Symposium. He is a Life Fellow of the IEEE; was a Fulbright-Hays scholar (1972); received the 1991 Associates Award for Creativity in Research and Scholarship from the University of Southern California, the 1991 USC School of Engineering Award for Exceptional Service, the IEEE Computer Society’s 1993 Taylor L. Booth Education Award, an Okawa Foundation Research Grant in support of research to “Increase the effective yield of VLSI chips via design and test” (2003), and the first (2000) Engineering Faculty Council Award for Outstanding Meritorious Service to the USC School of Engineering. He was the keynote speaker at the Fourth Multimedia Technology and Applications Symposium, 1999; the Ninth Asian Test Symposium, 2000; the International Conference on Computer Design (ICCD), 2004; the Annual Symposium on VLSI (ISVLSI), 2005; the IEEE VLSI Test Symp., 2008, and an invited speaker at the Thirteenth Asian Test Symposium, 2004. The Test Technology Technical Council of the IEEE Computer Society hosted a forum on October 26, 2006 at the Hyatt Regency Hotel, Santa Clara, California to “celebrate Professor Melvin A. Breuer’s illustrious career and recognize his contributions to VLSI areas of design automation, design for testability, fault tolerance and test; and the influence he had on the industry and academia as an educator and a mentor.”

 

 

 

 

Cavium Networks

 

YJ Kim is the General Manager of the Infrastructure Processor Group at Cavium Networks.

 

 

4G SoC Technology Innovation, from 150Mb UL small cell to 100Gb EPC.
 

 

Abstract: With the complexity and bandwidth requirements of 4G wireless, industry needs a processor family that can address both compute, throughput, services, power, cost and scalability as well as full software re-usability top-to-bottom from mobile access to mobile core network equipment. Cavium will be disclosing comprehensive 4G Mobile access and core processors and partner solutions for 4G Wireless Carrier segment, including market winning 4G small cell and macro cell SoCs, 4G LTE Evolved Packet Core/ WiMAX ASN Gateway 100Gb processors, industry leading 4G Gateway ATCA/ODM platforms and comprehensive 4G wireless software stacks. Will include demonstrations of smallcell and EPC performances.

 

Bio: YJ Kim is the General Manager of the Infrastructure Processor Group at Cavium Networks, responsible for the OCTEON Multi-core Processor business and product lines. Since joining the company in June 2006, he has rapidly established OCTEON as the leader in multi-core solution in wireless infrastructure markets. YJ is a veteran in the microprocessor and networking industry with over 22 years of experience. Prior to joining Cavium Networks, Mr. Kim held several key roles in the industry, including General Manager/Core Team Lead of Tolapai (IA SOC – EP80579) at Intel Corp, Co-founder/Director at API Networks, a company that achieved $230M revenue at exit, Marketing Director at Samsung Semiconductor and various marketing manager positions in the Westport/IXP2350, Intel x86 Microprocessor and Flash groups. YJ holds a B.S.E.E. and Master of Engineering in E.E. from Cornell University, and has attended Wharton Executive Program at University of Pennsylvania.

 

 

 

Afternoon Break

Afternoon Break

 

 

UCSD

 

 

Houman Homayoun, PhD, NSF-CRA Computing Innovation Fellow University of California, San Diego Department of Computer Science and Engineering.

 

 

Dynamically Heterogeneous Cores Through 3D Resource Pooling.
 

 

Abstract:  This work describes an architecture for a dynamically heterogeneous processor architecture leveraging 3D stacking technology. Unlike prior work in the 2D plane, the extra dimension makes it possible to share resources at a fine granularity between vertically stacked cores. As a result, each core can grow
or shrink resources, as needed by the code running on the core. This architecture, therefore, enables run-time customization of cores at a fine granularity, enables efficient execution at both high and low levels of thread level parallelism, enables fine-grain thermal management, and enables fine-grain reconfiguration around faults. With this architecture, we achieve performance gains from 9-41%, depending on the number of executing threads, and gain significant advantage in energy-efficiency.


Bio:  Houman Homayoun received the PhD degree from the department of computer science at the University of California Irvine in 2010. He named a 2010 National Science Foundation Computing Innovation Fellow by the Computing Research Association (CRA) and the Computing Community Consortium (CCC).  He is currently working with Dean Tullsen at UC-San Diego. He was a recipient of the 4-years UC-Irvine computer science department chair fellowship. His research is on power-temperature and reliability-aware memory and processor design optimizations and spans the areas of computer architecture, circuit design and VLSI-CAD, where he has published more than 30 technical papers on the subject. His research is among the first in the field to address the importance of cross-layer power and temperature optimization in memory peripheral circuits. The results of his research were published in top-rated conferences/journals including DAC, DATE, ISLPED, ICCD, CASES, HiPEAC, LCTES, and TVLSI. He received his BS degree in electrical engineering in 2003 from Sharif University of technology, Tehran, Iran. He received his MS degree in computer engineering in 2005 from University of Victoria, Canada.

 

 

 

Movidius Ltd.

 

Dr. David Moloney, CTO, Movidius Ltd.

 


Greening Multicore – Maximizing Performance/Watt Embedded Multicore Software Development – Lessons from the Trenches.

 

Abstract: Movidius is a fabless semiconductor company based in Dublin, Ireland and established in 2005. Since inception the company vision was to radically change the approach to providing multimedia functionality in mobile devices. To date this approach has consisted on one or more processors augmented by DSP and fixed-function cores. Having evaluated the available cores and the emerging multimedia requirements Movidius decided to build a new processor and multicore architecture optimized from the ground up for power efficiency. Movidius SHAVE processor is a hybrid stream processor architecture combining the best features of GPUs, DSPs and RISC with both 8/16/32 bit integer and 16/32 bit floating point arithmetic as well as unique features such as hardware support for sparse data structures. The architecture is designed to maximise performance/watt while maintaining ease of programmability, especially in terms of support for design and porting of multicore software applications. The resulting architecture offers outstanding performance/watt across a very broad spectrum of applications from game-physics to 3D HD video encode on Movidius 65nm Myriad SoC containing 8 SHAVE processors as well as an on-board 32-bit RISC and numerous programmable peripherals. The detailed SHAVE architecture as well as unique features will be presented, along with the SoC implementation details including power optimization and power-saving features of the Myriad SoC. Results based on silicon will be outlined in comparison to the state-of-the-art and preliminary. Details of Movidius software development flow and applications as well as product roadmap will be outlined. 

 

Bio:  David Moloney received a B.Eng from Dublin City University in 1985, and Ph.D. in Engineering from Trinity College Dublin in 2010. Since 1985 he worked for Siemens Halbleiter AG (Infineon) in Munich and ST Microelectronics in Milan as a DSP IC designer, before returning to Ireland 1994 to co-found a series of start-up technology companies including Parthus (CEVA) and Silansys (Frontier-Silicon). David is currently co-founder (2005) and CTO of Movidius Ltd., a fabless semiconductor company headquartered in Dublin and focused on the design of software programmable multimedia accelerator SoCs. He holds 18 US patents with many others in process as well as authoring conference and journal papers on DSP and computer architecture. David is a member of the IEEE.

 

 

 

10 Min

Afternoon Break

 

10 Min

Afternoon Break

 

     

 

Panel

 

(FREE for Everyone!)

 

 

“Technology & Entrepreneurship: Dreams, Realities & Opportunities”

 

Open To Everyone

 

     

 

Savant Company Inc.

 

 

Netvinci Inc.

 

Source Scientific

 

Stetina Brunda Garred & Brucker.

 

Hiperwall

 

Excalibur Engineering

 

Corporate Finance Associates

 

Farhad Mafie, SoC Conference Chairman, Savant Company Inc., President & CEO,  IEEE OC SSCS & OCEN Chairs.

 

Moderator
 

Bio: Farhad Mafie is President and CEO of Savant Company Inc., a technology marketing company in Irvine, CA. Savant specializes in marketing and sales of semiconductor IC/IP products, SoC/ASIC services and solutions, as well as providing targeted technical- and business-related training seminars and conferences globally. He has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience. He is the former Vice President of Marketing and Engineering at Toshiba Semiconductor. He has also worked in strategic marketing, project and design engineering at Lucent Technologies, Unisys, and MSI Data. Farhad has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton. He is an author and a translator, and his articles have been published in a variety of journals and Web-based magazines on technology and political affairs. In 2003, he published the biography of Iranian poet and Nobel nominee who lived in exile, Nader Naderpour (1929-2000), Iranian Poet, Thinker, Patriot. Farhad is also Editor-in-Chief for the CRC Press SoC Design and Technologies Book Series, which includes (1) Low-Power NoC for High-Performance SoC Design and (2) Design of Cost-Efficient Interconnect Processing Units. Farhad is an active member of IEEE, and he is the chair of IEEE Orange County Solid-State Circuits Society (SSCS), as well as IEEE Orange County Entrepreneurs' Network (OCEN). He is also a member of two UCI Advisory Committees: Communication System Engineering and Embedded System Engineering Certificate Programs. 

 

 

 

Panelists:

 

1. Bruce Sargeant, Founder, President & CTO, Source Scientific.  

2. Jeff Greenberg, CEO, Hiperwall.

3. Eric Tanezaki, Intellectual Property Law Partner, Stetina Brunda Garred & Brucker.

4. Jauher Zaidi, Chairman & CEO, Netvinci Inc.

5. Chris LaPlante, Founder & President, Excalibur Engineering.

6. Peter Heydenrych, Chairman and CEO, Corporate Finance Associates. 

 

This Panel Is Open To Everyone . . .  Register for FREE Panel Pass

 

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Several Opportunities to Win various Prizes During this Panel Discussion . . .

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Source Scientific.

 

Bruce Sargeant, Founder, President and CTO of Source Scientific in Irvine.   
 


Panelist

 




Bio: Mr. Sargeant has over 30 years of engineering product development and management experience. As a serial entrepreneur, Bruce has founded and managed five medical/fitness based device companies over the past 31 years. His companies have developed products such as clinical diagnostic instruments, ultrasound ablation systems, patient monitors, cardioplegia pump control systems, pH sensors, and computer controller fitness equipment. Bruce holds 9 US patents and earned his BSEE from California State University, Long Beach. He was named its most distinguished alumnus in 1983. He is currently President and CTO of Source Scientific in Irvine, Calif.
 

     

 

Hiperwall

 

Jeff Greenberg, CEO, Hiperwall.   
 


Panelist

 




Bio: Jeff Greenberg is CEO of Hiperwall, a UCI spinoff whose innovative software eliminates the cost and complexity of traditional hardware-based video-wall and distributed visualization systems, while providing additional unique capabilities. Greenberg has over 25 years of experience in Orange County’s high-tech community. He holds B.S. and M.S. degrees in computer science as well as an MBA. In his spare time he teaches entrepreneurship, serves as Entrepreneur-in-Residence for UCI’s Don Beall Center for Innovation and Entrepreneurship, and has been published in technology and business publications like PC Magazine and US News and World Report.
 

     

 

Stetina Brunda Garred & Brucker

 

Eric Tanezaki, Intellectual Property Law Partner, Stetina Brunda Garred & Brucker.
 

 

Panelist

 

 

Bio: Eric is a partner of Stetina Brunda Garred & Brucker, a boutique full service intellectual property law firm. He has represented numerous companies in various industries in relation to patent, trademark and copyright matters, seeking rights as well as related licensing. He received his undergraduate engineering degree from the University of Southern California, and his law degree from the McGeorge School of Law, University of the Pacific. Prior to law school Eric worked in the aerospace industry. Eric is the Executive Director of the Southern California Venture Network (SCVN.org). In addition, Eric is the IP Law Mentor to the USC Stevens Institute for Innovation.

     

 

Netvinci Inc.

 

Jauher Zaidi, Chairman & CEO, Netvinci Inc.

 

 

Panelist

 

 

Jauher Zaidi is Chairman & CEO of Palmchip Corporation.  Jauher has over twenty years of experience in system design and integration. Before founding Palmchip in 1996, he was involved in system-on-chip (SoC) integration at Quantum Corporation. Jauher received his BSEE and MSEE degrees from Pacific States University in Los Angeles, California. He has also participated in many SoC panels and is a recognized expert in the area of SoC development. 

     

 

Excalibur Engineering

 

Chris LaPlante, Founder & President, Excalibur Engineering.  
 


Panelist

 

 

 


TBA.

 

     

 

Corporate Finance Associates

 

Peter Heydenrych, Chairman and CEO, Corporate Finance Associates
 


Panelist

 


Bio: Peter Heydenrych is Chairman and CEO of Corporate Finance Associates. With more than 20 years experience in corporate finance and investment banking, including international banking and M&A, he draws on a depth of experience and brings important insights to bear on the issues faced by clients. Peter’s entrepreneurial experience, as the owner of both service and manufacturing companies, provides added perspective and an enhanced ability to execute successful transactions, serving clients through a thorough understanding of both the process and the anatomy of M&A transactions. Most importantly, Peter’s acknowledged capabilities make him a highly skilled negotiator who is analytical and tenacious, yet objective and fair.  Peter began his work in M&A when, as a Partner and the Managing Director of one of the largest U.S. architecture firms, he represented the company in a highly strategic sale to a Fortune 100 company. He transferred to the acquiring company, and implemented a national roll-up of interior architecture & design and furniture distribution companies.  Peter joined Corporate Finance Associates in 1991, and was a member of the management team which completed a buyout of the firm in 1996. He has participated in numerous M&A and corporate finance transactions, representing parties wishing to sell, buy or capitalize middle market businesses. Building on corporate affiliations and M&A experience, Peter has served the needs of middle-market companies in the technology, health, business services, transport, telecommunications, manufacturing, financial services and construction industries. Peter is a Chartered Accountant of South Africa and holds a Masters Degree in Business Administration from the University of Cape Town, South Africa. Peter holds FINRA Series 7, 79, 24, 28 and 63 licenses.

 

     

 

 

 

Open To Everyone

 

Reception

 

&

 

 Networking

 

 

 

 

 

 

9th International SoC Conference Closed.

 

 

 

 

 

 

 

* Program is subject to change. SoC Conference Organizing Committee, Technical Advisory Board (TAB), and Savant Company Inc. reserves the rights to revise or modify the SoC Conference program (the above program) at its sole discretion.

 

 

 

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