7th International SoC Conference


	Schedule & Program Summary
SoC Conference Day 1	Wednesday, November 4, 2009	8:00 am - 5:30 pm
SoC Conference Day 2	Thursday, November 5, 2009	8:00 am - 7:00 pm
SoC Tabletop Exhibit & Reception	Wednesday, November 4, 2009	3:00 pm - 8:00 pm
SoC Workshops	Check the Individual Workshop Schedules
Job Fair	Wednesday, November 4, 2009	3:00 pm - 8:00 pm
Student Design Contest	Wednesday, November 4, 2009	7:00 pm - 7:30 pm

SoC Conference Program Agenda*


Day One Wednesday November 4	Session	Company or University
7:00 am – 6:00 pm	Registration Open All Day Several Opportunities to Win various Prizes Throughout the Conference Program . . . Don't Miss Out!
8:00 - 8:10	Welcome, Opening Remarks, and Conference Updates. Farhad Mafie, President and CEO.	Savant
	Complex SoCs & New Trends, Technologies & Market Opportunities Track Chairman: Farhad Mafie.
8:10 - 8:40	Low Power Design Techniques - Verification Challenges, Dr. Shireesh Verma, Imaging and PC Media Group.	Conexant Systems, Inc.
8:40 – 9:10	Designing In Hardware Root of Trust for Embedded Systems, Dan O’Loughlin, Sr. Director of Product Management. Certicom Corp., a subsidiary of RIM Corporation	Certicom Corp
9:10 – 9:40	A New Breed of ASIC for Networking Markets, Robert Madge, Director of Technology Marketing.	LSI Corporation
9:40 – 10:10	CMOS and MEMS Integration: The next frontier in cost and performance optimization, Mark A. Miller, V.P. Business Development.	X-Fab Semiconductor Foundries
10:10 - 10:20	Morning Break
10:20 – 11:00 Keynote	Keynote: Dr. Juan-Antonio Carballo, Venture Strategy Executive, IBM.	IBM
11:00 - 12:00 Panel	Panel: "Exploring Opportunities for the Integration of Silicon and Biotechnology" Moderator: Mark A. Miller, V.P. Business Development. X-Fab Semiconductor Foundries. Panelists: 1. Professor Alice C. Parker, The BioRC Biomimetic Real-Time Cortex Project, Department of Electrical Engineering, USC. 2. Professor Yu-Hwa Lo, Department of Electrical and Computer Engineering, Specializes in Photonic Integrated Circuits, UCSD. 3. Dr. Jim Brody, Associate Professor Biomedical Engineering, UCI. 4. Chi On Chui, Ph.D., Assistant Professor of Electrical Engineering, UCLA. 5. Mohammad E. Kondri, MPH, MIS/MBA, International Business Development Officer, Trade Commissioner, Life Sciences & Medical Technologies, Canadian Consulate General. 6. TBA Several Opportunities to Win various Prizes During this Panel Discussion . . . Don't Miss Out!	X-Fab Semiconductor Foundries USC UCSD UCI UCLA Canadian Consulate General
12:00 pm - 1:00 pm	Lunch
1:00 - 2:00 Panel	Panel: “Improving Design Productivity and IP Quality through the Effective Use of Standards for Complex Multicore SoCs" Moderator: Dr. J. Antonio Carballo, WW Manager, IBM Microelectronics Services, Semiconductor Partner, IBM VC Group. Panelists: 1. Dr. Karen Pieper is Director of Synthesis at Tabula Inc. & Technical Chair for Accellera. 2. Dr. Gary Delp, VP and Technical Director of the SPIRIT Consortium and Principal of the consulting firm Silver Loon Systems. 3. Warren Savage, President & CEO. IPextreme. 4. Michael Brunolli, Co-Founder and CTO, Rapid Bridge. 5. Ken Brock, Product Line Director. Virage Logic 6. Ravi Thummarukudy, VP& GM, IC Solutions Business Unit and Co-Founder, GDA Technologies. Several Opportunities to Win various Prizes During this Panel Discussion . . . Don't Miss Out!	IBM Virage Logic Accellera Tabula Inc. SPIRIT Consortium IPextreme GDA Technologies Rapid Bridge
2:00 - 2:40 Keynote	Keynote: Ken Hansen, Sr. Fellow, Vice President and Chief Technology Officer (CTO).	Freescale
2:40 - 2:50	Afternoon Break
	Innovative IPs and Design Challenges in Complex Multicore SoCs Track Chairman: Farhad Mafie
2:50 – 3:20	ASIPs: Programmable Accelerators for Multicore SoCs, Steve Cox & Gert Goossens, - Leuven, Belgium and Boulder, CO USA.	Target Compiler Technologies
3:20 – 3:50	Via-configurable, mixed-signal embedded ASICs using the ARM Cortex-M0 microcontroller, Jim Kemerling, CTO.	Triad Semiconductor, Inc.
3:50 – 4:20	System-Level Performance Analysis of ARM based SoCs, Dr. Mrinmoy Ghosh, Research and Development.	ARM
4;20 – 4:50	MCST-4R – SPARC-V9 compatible scalable SoC design, Sergey A. Cherepanov, Technical Lead.	MCST (Russia)
4:50 – 5:20	IP for Video Compression Decoder (H.264), John Johl, Advanced Architectures.	PixSil Technology Corporation
3:00 pm - 8:00 pm Exhibit Reception & Job Fair	Conference Exhibit & Reception Open (Free Exhibit Pass, Free Parking, Many Door Prizes) Including IEEE Sponsored Student Design Contest IEEE Tech Job Fair (In Adjacent Ballroom) Several Opportunities to Win an iPod shuffle During the Exhibit Reception . . .


Day Two Thursday November 5	Session	Company or University
7:00 am – 7:00 pm	Registration Open All Day
8:00 - 8:10	Welcome, Opening Remarks, and Conference Updates. Farhad Mafie, President and CEO.	Savant
8:10 – 8:40	Advanced Multitasking - Do More, Work Less, Be Happy. Mike Sanders, PMP.	Southern California Edison
	NoC (Network-on-Chip), New Approaches, Solutions, and Challenges for Complex Multicore SoCs Track Chairman: TBA
8:40 – 9:10	Simple and Efficient Implementation of Virtual Channels for NoCs, Francisco Gilabert. Parallel Architectures Group – UPV - Spain & MPSoC research group – UNIFE – Italy.	Technical University of Valencia (Spain)
9:10 – 9:40	Characterizing random variations in NoC links, Carles Hernández & Federico Silla.	Technical University of Valencia (Spain)
9:40 – 10:10	Is Network-on-Chip (NoC) a Viable Choice for the Future? Dr. Nader Bagherzadeh, professor of computer engineering in the department of electrical engineering and computer science, University of California, Irvine.	University of California, Irvine.
10:10 – 10:20	Morning Break
10:20 – 11:00 Keynote	Keynote: Beyond the Power and Memory Walls: The Role of NoCs in Future System Architectures. Professor Jose Duato.	Technical University of Valencia (Spain)
11:00 – 12:00 Panel	Panel: “Green Chips: Technology, Trends, and Challenges in Low-Power Multicore SoC Designs” Moderator: Steve Leibson, EDN, Marketing Consultant and Contributing Editor Magnetic Marketing and Persuasive Communications. Panelists: 1. Dr. Barry Pangrle, Solutions Architect, Low Power, Design and Verification, Mentor Graphics. 2. Michel Laurence co-founded Octasic. 3. Dr. Siamack Haghighi, Principal Architect in QCT (Qualcomm CDMA Technology) Architecture group, Qualcomm. 4. Jauher Zaidi, CEO, PalmChip Corporation 5. Alan Ruberg, SPMT architect for SPMT, The Serial Port Memory Technology consortium. 6. TBA. Several Opportunities to Win various Prizes During this Panel Discussion . . . Don't Miss Out!	EDN Savant Company Inc. Qualcomm Mentor Graphics Octasic SPMT PalmChip Corporation
12:00 – 1:00	Lunch
	Innovative Tools & Methodologies for Complex SoC Designs. Track Chairman: TBA
1:00 – 1:30	Elements of the architectural design renaissance, Steven Carlson VP Product Marketing.	Cadence Design Systems
1:30 – 2:00	Improving Verification Efficiency with Rule Based Automatic Formal Analysis, Dr. Pranav Ashar, CTO.	Real Intent
2:00 – 2:30	Wide Scale Acceptance of Assertion Based Verification, Howard L. Martin, Founder and President.	Zocalo Tech, Inc.
2:30 – 3:00	How to tackle variability on advanced 32nm design, Rahul Deokar, Product Director.	Cadence Design Systems
3:00 – 3:15	Afternoon Break
3:15 – 3:45	Clock Concurrent Timing Optimization, Rethinking Timing Optimization to Target Clocks and Logic at the Same Time, Marc Swinnen, Director of Product Marketing.	Azuro Inc.
3:45 – 4:15	I/O Fabric and I/O Control Logic Validation of a Multi-million Gate Low Power SoC: Challenges and Solution, Deepak Agarwal, Senior Design Engineer.	Texas Instruments
4:15 – 4:45	New Design Techniques Enabling Mixed-Signal IP Integration In the 32/28 nm SoC Era, Navraj Nandra, Director of Mixed-Signal IP.	Synopsys
4:45 – 4:50	Afternoon Break
4:50 – 5:50 Panel "FREE"	Panel: “Technology & Entrepreneurship: Dreams, Realities & Opportunities” Moderator: Dr. Goran Matijasevic is Director of Research Development at The Henry Samueli School of Engineering at UC Irvine. Panelists: 1. Michael Hajeck, Senior Vice President & General Manager Solid State Storage Business Unit Western Digital, Former Silicon Systems CEO. 2. Richard Henson, CEO & Founder, Source Scientific. 3. Eric Tanezaki, Intellectual Property Law Partner, Stetina Brunda Garred & Brucker. 4. P. K. Shukla, Ph.D., CPIM, Vice Chancellor for Entrepreneurship, Director, Leatherby Center for Entrepreneurship and Business Ethics, Chapman University. 5. Hamid Lalani, X/Seed Capital Management. This Panel Is Open To Everyone . . . Register for FREE Panel Pass More Updates Coming Soon . . . Several Opportunities to Win various Prizes During this Panel Discussion . . . Don't Miss Out!	UC Irvine Chapman University Brandman University Western Digital Source Scientific TETINA BRUNDA GARRED & BRUCKER X/Seed Capital Management Savant Company Inc.
5:50 – 6:30	Open To Everyone Reception & Networking	Savant
	7th International SoC Conference Closed.