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Registration Is Now
Closed!
Keynotes & Panels
17th International System-on-Chip
(SoC)
Conference, Exhibit & Workshops
The Theme for This Year’s
Conference Is “Silicon Engineering The Future."
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Directions &
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Schedule & Program Summary
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SoC Conference Day 1 |
Wednesday, October 16, 2019
UCI - Calit2 Building |
8:00 am - 7:00 pm |
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SoC Conference Day 2 |
Thursday, October 17, 2019
UCI - Calit2 Building |
8:00 am - 6:30 pm |
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Tabletop Exhibition,
SoC Student Design Contest &
Reception (at 6 pm) - Open to Public. |
Wednesday, October 16, 2019
UCI - Calit2 Building |
2:00 pm - 7:00 pm |
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Google
Keynote
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Dr.
Martin Maas, Research Scientist, Google Research, Brain Team.
“TBA"
Abstract: TBA
Bio: Research Scientist in the
Google Brain team. Before joining Google, I completed my PhD in the
Electrical Engineering and Computer Sciences department at UC Berkeley,
working with Krste Asanović and John Kubiatowicz. My primary research
interests are in managed language runtime systems, operating systems and
computer architecture. I am interested in the entire stack from the hardware
to the programming systems layer. At Google Brain, I am working on topics
related to machine learning. My PhD research focused on warehouse-scale
computers. I worked and collaborated across areas and built real systems
that involve large system-level codebases as well as hardware-level RTL. I
have applied this approach to domains ranging from security to managed
languages. During my PhD, I built a secure processor that provides
memory-trace obliviousness (a new security property) and can be targeted by
a custom compiler, a distributed language runtime system that coordinates
JVMs on different nodes in a cluster, and worked on hardware support for
garbage collection. I have also built research infrastructure, including
FPGA implementations of hardware based on the RISC-V ISA. Before
coming to UC Berkeley, I completed my undergraduate degree at the University
of Cambridge. In my undergraduate research, I investigated the challenges
and bottlenecks of implementing a Java Virtual Machine for the Barrelfish
Operating System. I was supervised by Ross McIlroy and Tim Harris from
Microsoft Research, Cambridge. During my time in high-school, I
was an active participant in science and programming competitions. I was on
the German team for the International Olympiad of Informatics (IOI) and
represented Germany at the International Science and Engineering Fair (ISEF).
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Intel
Keynote
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Sailesh
Kottapalli, Intel Senior Fellow, Intel Architecture, Graphics and Software
Chief Architect, Datacenter Processor Architecture.
“Computing Infrastructure in
Data-centric era"
Abstract: Computing
infrastructure is increasingly influenced by the need to manage the
exponential growth in data. The computing infrastructure needs to move this
massive amounts of data, store it and harvest it by processing for value
added insights that drive business value by delivering to customer’s needs.
This is driving changes across the entire spectrum of Computing,
interconnects, memory and storage as well as security requirements. In
addition, how we deliver that value across architecture, SW, design, process
and packaging is also changing. This talk will outline a number of trends as
a result and the specific solutions and SoC architecture to address these
trends.
Bio: Sailesh Kottapalli, Intel
Fellow, Platform Engineering Group Director, Data Center Processor
Architecture, joined Intel in 1996 as a design engineer working on the first
Intel® Itanium® processor, then code-named "Merced." Subsequently, he served
as lead engineer for several Intel Itanium and Intel Xeon processor
evaluations, and more recently, as lead architect for a series of Intel Xeon
server processors. His work in this area earned Kottapalli an Intel
Achievement Award for delivering record generational performance
improvements in a high-end server product. An active participant in industry
and internal conferences, Kottapalli has authored or co-authored several
published technical papers, delivered talks and taken part in roundtables
and panel discussions. He has also been granted approximately three dozen
patents in processor architecture, with additional patents pending.
Kottapalli holds a bachelor's degree in computer science from Andhra
University in India and a master's degree in computer engineering from
Virginia Tech.
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University of Texas at Austin
Keynote
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Dr.
Lizy Kurian John, P.E., The Cullen Trust for Higher Education Endowed
Professor in Engineering No.3, IEEE Fellow.,
University of Texas at Austin.
"Machine
Learning for Performance and Power Modeling / Prediction."
Abstract: Estimating the
power and thermal characteristics of SoCs is essential for designing its
power delivery system, packaging, cooling, and power/thermal management
schemes. Power models that estimate the power consumption of each functional
unit/hardware component from first principles are slow and tedious to build.
Machine learning can be used to create power models that are fast and
reasonably accurate. Machine learning can also be used to calibrate
analytical models that estimate power. In this talk, I’ll present some
examples of performance and power modeling using machine learning. Another
application for machine learning has been to create max power stressmarks.
Manually developing and tuning so called stressmarks is extremely tedious
and time-consuming while requiring an intimate understanding of the
processor. In our past research, we created a framework that uses machine
learning for the automated generation of stressmarks. In this talk, the
methodology of the creation of automatic stressmarks will be explained.
Experiments on multiple platforms validating the proposed approach will be
described. Yet another application for machine learning is in cross-platform
performance and power prediction. If one model is slow to run real-world
benchmarks/workloads, is it possible to predict/estimate the
performance/power by using runs on another platform? Are there correlations
that can be exploited using machine learning to make cross-platform
performance and power predictions? A methodology to perform cross-platform
performance/power predictions will be presented in this talk.
Bio: Dr. Lizy Kurian John
holds the Cullen Trust for Higher Education Endowed Professorship in
Electrical Engineering in the Department of Electrical & Computer
Engineering at The University of Texas at Austin. She received her Ph.D. in
computer engineering from The Pennsylvania State University. She joined The
University of Texas Austin faculty in 1996. Her research is in the areas of
computer architecture, multicore processors, memory systems, performance
evaluation and benchmarking, workload characterization, and reconfigurable
computing. Professor John's research has been supported by the National
Science Foundation, Semiconductor Research Consortium (SRC), DARPA, Lockheed
Martin, AMD, Oracle, Huawei, IBM, Intel, Motorola, Freescale, Dell, Samsung,
Texas Instruments, etc.. She is recipient of NSF CAREER award (1996), UT
Austin Engineering Foundation Faculty Award (2001), Halliburton, Brown and
Root Engineering Foundation Young Faculty Award (1999), University of Texas
Alumni Association Teaching Award (2004), The Pennsylvania State University
Outstanding Engineering Alumnus (2011) etc. Professor John holds 10 U. S.
patents and has published 16 book chapters, 200 refereed journal and
conference publications, and approximately 50 workshop papers. She has
coauthored books on Digital Systems Design using VHDL (Cengage Publishers),
Digital Systems Design using Verilog (Cengage Publishers) and has edited a
book on Computer Performance Evaluation and Benchmarking (CRC Press). She
has also edited three books on workload characterization. Professor John is
the Editor-in-Chief (EIC) Elect of IEEE MICRO (term begins January 2019) and
she is in the editorial boards of ACM Transactions on Architecture and Code
Optimizations (TACO), IEEE Computer Architecture Letters, IEEE Transactions
on Sustainable Computing, and has served in the past as an associate editor
of IEEE Transactions on Computers and IEEE Transactions on VLSI. She is a
member of IEEE, IEEE Computer Society, ACM, and ACM SIGARCH. She is an IEEE
Fellow (Class of 2009). |
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IBM
Keynote
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Jason
S. Miller, Director, IBM Z Processor and Systems Chips Development.
"The Technology Behind the
Latest IBM Z Mainframe"
Abstract: Mainframes are the
IT foundation of the global economy. Every day, over $25B of credit card and
ATM transactions flow through the platform, as well as millions of airline
reservations, hotel bookings, car rentals, etc. In this talk, we will look
at the custom silicon technology that powers this essential platform,
including the ultra high-frequency central processor, the custom I/O data
routers, and the industry-leading hardware encryption engines. Included in
this talk will be a discussion of the pre-silicon verification methodologies
that enable us to bring highly complex processors and SOCs to market in
record time.
Bio: Jason Miller is the Director of IBM Z Processor and Systems Chips
Design at IBM. He leads a global team responsible for designing and bringing
to market the industry-leading high performance processors and SOCs that
power IBM Mainframes. Prior to this role, Jason led Procurement Engineering
for IBM, supporting all procured hardware components and technologies for
IBM Systems. Over his career, Jason has held numerous roles in Systems
Hardware Development, ASIC Design, Semiconductor Manufacturing, and
Microelectronic Packaging. Jason joined IBM in 2000. He holds a BS in
Mechanical Engineering from Penn State University.
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Xilinx
Keynote
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Jennifer
Wong, Vice President of FPGA Product Development. Xilinx Inc.
"A Holistic Approach for
System Integration and Performance Optimization."
Abstract: Rapid scaling with
Moore’s Law and the more recent 3DIC development have led to the shrinking
of electronic systems over the last several decades. As scaling continues
beyond single CMOS device to include heterogeneous devices in 2.5D and 3D
stacking, design methodologies need to keep pace to enable complex
integration to achieve optimal system performance. This requires a new
holistic approach for design optimization of the integrated silicon, package
and PCB leading to miniaturized solutions that have superior performance.
Bio: Jennifer Wong is Corporate Vice President of Silicon Integration at
Xilinx, where she is responsible for design methodology and chip-level
integration, as well as system signal/power integrity, package and
printed-circuit board development. She has contributed to over 8 generations
of FPGAs and SoCs at Xilinx. Before joining Xilinx, Jennifer was with
Advanced Micro Devices developing CPLDs. She received her Master of Science
and Bachelor of Science degrees, both in electrical engineering, from the
University of California, Berkeley. In addition, Jennifer has published
multiple papers and has earned 45 patents.
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Panel #1
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Wednesday,
October 16, at
1:00 PM
Panel #1 |
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Panel
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Panel: “RISC-V
Realities, Opportunities and Challenges in the Complex and Crowded CPU
Market."
Moderator: Farhad Mafie, SoC Conference Chairman.
Panelists:
1. Dr. Rob Aitken, R&D Fellow and technology lead for Arm Research, ARM.
2. Nader Bagherzadeh, Professor (Joint Appointment), Electrical Engineering
and Computer Science & Donald Bren School of Information and Computer
Science. University of California, Irvine.
3. Grant Martin, Distinguished Engineer, Tensilica R&D - Cadence Design
Systems.
4. Dr. Emerson Hsiao, Senior VP, Andes Technology USA Corp.
5. Wayne Radochonski, CTO, Pixilica.
6. Gerald D. Zuraski Jr., Senior Principal Engineer, Austin R&D Center,
Samsung.
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Panel #2
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Wednesday,
October 16, at
5:00 PM
Panel #2 |
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Panel
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Panel: “How AI and Machine Learning will Drive the
Semiconductors Market to the Next Level."
Moderator: Farhad Mafie, SoC Conference Chairman.
Panelists:
1. Dr. Jun Miyazaki, CEO and Founder OrangeTechLab Inc.
2. Dr. Tirthajyoti Sarkar, Sr. Principal Engineer, AI/Machine Learning, ON
Semiconductor.
3. Iman Khabazian, CTO, Vairtis Corporation.
4. Anil Mankar, COO & SVP Engineering, BrainChip Inc.
5. Alvin Joseph, CIO, VP Information Technology, Orora.
6.
Dr. David Garrett, VP
Hardware, Syntiant.
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Panel #3
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Thursday,
October 17, at
5:00 PM
Panel #3 |
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Panel
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Panel:
“Is Blockchain of Things IoT 2.0? Could Blockchain of Things be the Security
solution that the industry has been looking for?"
Moderator: Farhad Mafie, SoC Conference Chairman.
Panelists:
1. Dr. Pim
Tuyls, Founder and Chief Executive Officer, Intrinsic ID.
2. Marc Canel, Vice President of Strategy – Security at Imagination
Technologies.
3. Jauher Zaidi, Chairman & Chief Innovation Officer, Palmchip Corporation.
4. Chad Blickenstaff, Enterprise Resource Manager, Oracle.
5. Pamela Norton, CEO and Founder, Borsetta.
6. TBA.
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