10th International SoC Conference


	Microsemi Keynote	Jim Aralis, Chief Technology Officer (CTO), and Vice President of R&D. Keynote: “A New Paradigm: Disruptive SoC Design & Market Strategies.” Bio: Jim Aralis has served as chief technology officer and vice president of R&D for Microsemi since January 2007. He has more than 30 years experience in developing custom analog device and process technologies, analog and mixed-signal ICs and systems, and CAD systems. Jim played a key role in transitioning Microsemi to a virtually fabless model, supporting multiple process technologies including, high voltage and high power BCD/CMOS, high power high integration CMOS, GaAs, SiGe, IPD, RF CMOS SoI, GaN, SiC, and several high-density packaging technologies. From 2000 to 2007, Jim established and served as senior design director of Maxim Integrated Product’s engineering center in Irvine, Calif. Before that, he spent 7 years with Texas Instruments/ Silicon Systems as mixed-signal design head and senior principal engineer. Additional experience includes 11 years with Hughes Aircraft Company in positions of increasing responsibility including senior scientist. Jim earned a bachelor of science degree in Math Applied Science and Physics and a master of science in electrical engineering from UCLA. He holds 9 patents for circuit and system design. Abstract: TBD.
	JPL Keynote	Dr. Reza Ghaffarian, Jet Propulsion Laboratory, California Institute of Technology. Keynote: "FPGA Packaging Trend and System Approach for Reliability." Bio: Dr. Reza Ghaffarian has more than 30 years of industrial and academic experience. For the last 19 years at NASA/JPL, he led R&D reliability and quality assurance activities in advanced electronic packaging and has been a consultant resource for most JPL projects including Mars Curiosity Rover. He received many award including the NASA Exception Service Medal for outstanding leadership and industrial partnership. He has authored more than 150 technical papers, co-editor of a CSP book, 7 book chapters, and two guidelines. He serves as technical Advisor/Committee to IPC, Microelectronics Journal, SMTA, IMAPS and IEEE IEMT/CPMT. He received his Ph.D. in 1982 from University of California at Los Angeles (UCLA). Abstract: Commercial-off-the-shelf column grid array packaging (COTS CGA) technologies in high reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. This presentation reviews technology of IC packaging developed to meet demands of high processing powers, which come in area array packages. It then provides a more detail discussion on using field programmable gate array (FPGA), which enable programmer to modify software on-the-spot during product use. The FPGAs come in area array packages now have more than thousand solder balls/columns under package area not only need to be correctly joined onto PCB; they also should show adequate system reliability meeting thermo-mechanical requirements for application. In addition, recent FPGA packages not only come with flip-chip with underfill exposed, they have decoupling capacitors on the package substrates that further added complexity. The key packaging trends and system reliability approaches with test data will be also presented.
	HP Keynote	Dr. Janice H. Nickel, Ph.D., Cognitive Systems Laboratory, Hewlett-Packard Laboratories. Keynote: “Making Memristors a Reality: Advances in Physical Understanding and Device Integration.” Abstract: Memristors are the fourth fundamental circuit element which was predicted in the early 1970’s and reduced to practice in 2008. Unlike capacitors or inductors, memristors do not store charge or energy, but do store information. This quality makes them a candidate for next generation memory technology, potentially replacing Flash and DRAM, whose ability to scale to future technology nodes is limited by the fact that they rely on stored charge. Because of the ability to create highly non-linear memristive devices, this technology is feasible for true crossbar memories –without requiring select transistors. This will not only permit highly dense, stackable memory, it also will enable integration of memristive memory with compute processors. In this talk I will define memristive systems, describe their electrical properties and how they differ from the three other fundamental passive circuit elements. I will highlight properties of memristive devices, including switching speed, switching energy and analogue operation. Advances in fabricating memristors in fully CMOS compatible materials and processes, as well as results from integrated CMOS + memristor crossbar structures from the SK Hynix – HP Joint Development will be presented. Possible future applications of the technology will be discussed. TBD Bio: Dr. Janice Nickel is a Research Manager in the Cognitive Systems Laboratory at Hewlett-Packard Laboratories. She obtained her BA in Physics, and PhD in Materials Science and Engineering, from the University of California at Berkeley, and has nearly 20 years industrial experience inventing, developing and transferring innovative products for a DOW 30 company. She is currently leading the memristor productization effort. In this capacity, she is directing HP’s participation in the joint development of the technology with SK Hynix, as well as creating proprietary CMOS compatible memristor fabrication processes. This effort leverages a her previous experience in the development of MRAM crossbar memory technologies. Prior to working on memristors, Dr. Nickel invented a unique programmable drug delivery platform – “Smart Drug Delivery” – which repurposes HP’s mature ink jet technology to address unmet pharmaceutical market needs. She catalyzed multiple business units in disparate geographic locations to develop component modules which she integrated into a proof-of-concept demonstrator. She created a business plan, attracted investors, and transferred the technology to the startup Janisys, Ltd. The Smart Drug Delivery technology won the 2007 Silicon Valley Business Journal’s Emerging Technology Award in Medical Devices, and was recognized in Popular Science’s “Best of 2008” in the Health category. Janisys is currently developing the technology in partnership with a major pharmaceutical company. Dr. Nickel has 45 U.S. Patents awarded, over 40 scientific papers published, and numerous invited presentations.
	Altera Keynote	Dr. Mike Peng Li, Fellow, Altera Corporation. Keynote: "FPGAs and the Era of Silicon Convergence." Abstract: Customer demand and the economies of the industry are driving a trend towards “silicon convergence.” Each new silicon process node allows chip designers to put more components-processors, accelerators, memory, and peripheral controllers, high-speed I/Os and photonic ICs-onto a single chip. More components means more capability, higher performance, higher throughput, lower power, and less area and space which are in high demand by system designers developing tomorrow’s cutting edge technologies. 3D and photonic enabled SoC FPGAs are leading the way in this trend and delivering customizable functionality and hardware acceleration for wired and wireless communications, computing, storage, military, industrial and automotive applications. Bio: Dr. Li has been with Altera Corporation since Sept., 2007 and currently is an Altera Fellow. He is a corporate expert and adviser, as well as CTO office principal investigator, on high-speed link/standards, SERDES architecture, electrical and optical signaling, silicon photonics, optical FPGA, high-speed debug and test, jitter, noise, signal and power integrity. He was the Chief Technology Officer (CTO) for Wavecrest Corporation from 2000-2007. Dr. Li is a Fellow of IEEE, and an affiliated professor at the Department of Electrical Engineering, University of Washington, Seattle. He holds a Ph.D. in physics (1991), an M.S.E (1991), in electrical and computer engineering and an M.S. in physics (1987), from the University of Alabama, Huntsville. He also holds a B.S (1985) in space physics from the University of Science and Technology of China. He was a Post Dr. and then a research scientist at the University of California, Berkeley (1991-1995).
	UCI Keynote	Dr. Payam Heydari, Nanoscale Communication Integrated Circuits (NCIC) Labs, University of California Irvine. Keynote: “Terahertz and Millimeter-Wave Imaging: New Frontiers of Electronics." Abstract: This keynote speech gives comprehensive overview of Terahertz and millimeter-wave (including both active and passive) imaging and their enabling and exciting applications. The speech then reviews current efforts to push the design of integrated circuits to operate at millimeter-wave and Terahertz frequency range. The talk covers daunting challenges in designing Terahertz building blocks and active/passive imaging systems at various levels of design hierarchy including system- and architecture-level down to the circuit- and device-levels. Bio: Payam Heydari (S’98–M’00–SM’07) received the B.S. and M.S. degrees (with highest honors) in electrical engineering from the Sharif University of Technology in 1992 and 1995, respectively. He received the Ph.D. degree in electrical engineering from the University of Southern California in 2001. Dr. Heydari is currently a Full Professor of Electrical Engineering and also School of Engineering Faculty Vice Chair. His research interests include the design of high-speed analog, radio-frequency (RF), and mixed-signal integrated circuits. He is the (co)-author of one book and 100 journal and conference papers. The Office of Technology Alliances at UCI has named Dr. Heydari one of 10 outstanding innovators at the university. Dr. Heydari is the co-recipient of the 2009 Business Plan Competition First Place Prize Award and Best Concept Paper Award both from Paul Merage School of Business at UC-Irvine. He is the recipient of the 2010 Faculty of the Year Award from UC-Irvine's Engineering Student Council (ECS), the 2009 School of Engineering Fariborz Maseeh Best Faculty Research Award, the 2007 IEEE Circuits and Systems Society Guillemin-Cauer Award, the 2005 NSF CAREER Award, the 2005 IEEE Circuits and Systems Society Darlington Award, the 2005 UCI’s School of Engineering Teaching Excellence Award, the Best Paper Award at the 2000 IEEE International Conference on Computer Design (ICCD), the 2000 Honorable Award from the Department of EE-Systems at the University of Southern California, and the 2001 Technical Excellence Award in the area of Electrical Engineering from the Association of Professors and Scholars of Iranian Heritage (APSIH). He was recognized as the 2004 Outstanding Faculty at the UCI’s EECS Department. Dr. Heydari’s paper entitled: Design of Ultra High-Speed Low-Voltage CMOS CML buffers and Latches, published in October 2004 issue of the IEEE Trans. on VLSI Systems, was ranked first among top downloaded articles in 2007. His research on novel low-power multi-purpose multi-antenna RF front-ends received the Low-Power Design Contest Award at the 2008 IEEE Int'l Symposium on Low-Power Electronics and Design (ISLPED). He is the co-founder of ZeroWatt Technologies, Inc., a fabless semiconductor startup in low power mixed signal integrated circuits design. Dr. Heydari is a Guest Editor of IEEE Journal of Solid-State Circuits. He currently serves on the Technical Program Committees of Compound Semiconductor IC Symposium (CSICS) and International Symposium on Low-Power Electronics and Design (ISLPED). He was an Associate Editor of the IEEE Transactions on Circuits and Systems – part I from 2006 to 2008. He was a Technical Program Committee member of the IEEE Custom Integrated Circuits Conference (CICC), and International Symposium on Quality Electronic Design (ISQED).