10th International SoC Conference


	Schedule & Program Summary
SoC Conference Day 1	Wednesday, October 24, 2012 Crystal Ballroom C & D	8:00 am - 5:00 pm
SoC Conference Day 2	Thursday, October 25, 2012 Crystal Ballroom C & D	8:00 am - 7:00 pm
SoC Tabletop Exhibit & Reception	Wednesday, October 24, 2012 Crystal Ballrooms A & B	3:00 pm - 8:00 pm
SoC Workshops	Check the Individual Workshop Schedules
IEEE-OC Tech Job Fair	Wednesday, October 24, 2012 Catalina Ballroom	3:00 pm - 6:00 pm
IEEE-OC Student Design Contest	Wednesday, October 24, 2012 Crystal Ballrooms A & B	6:00 pm - 7:30 pm

Day One OCT. 24, 2012 - SoC Conference Program Agenda*


Day One Wednesday October 24	Session	Company or University
7:00 am – 5:00 pm	Registration Open All Day Several Opportunities to Win various Prizes Throughout the Conference Program . . . Don't Miss Out!
8:00 - 8:10	"Welcome, Opening Remarks, and Conference Updates." Farhad Mafie, SoC Conference Chairman, IEEE OC SSCS & OCEN Chairs.	SoC Conference
	Analog and Mixed-Signal & SOI Design Trends and Challenges for Embedded Smart SoC Platforms Track Chairman: Dr. Janice H. Nickel, Ph.D., Cognitive Systems Laboratory, Hewlett-Packard Laboratories.
8:10 – 8:40	“CMOS Technology Scaling at 20nm and Beyond and Risk Management.” Horacio Mendez, Executive Director, SOI Industry Consortium.	SOI Industry Consortium
8:40 – 9:10	“Design Requirements For 28-nm and 20-nm Analog Mixed-Signal IP.” Navraj Nandra, Senior Director Marketing, Analog and Mixed-Signal IP.	Synopsys
9:10 – 9:40	“Solutions for the future challenges of computing: low power CMOS FDSOI and Silicon photonics +3D Heterogeneous integration.” Hughes Metras, VP, Strategic Partnerships, North America, CEA-LETI, France.	CEA-LETI France
9:40 – 10:10	“Integrating system I/O functions to increase system integration.” Paul Poenisch, Electrical Engineer working, Applications Group, X-FAB Semiconductor Foundries AG.	X-FAB Semiconductor Foundries AG
10:10 – 10:20	Morning Break
10:20 - 10:50	“Trends in Analog and Mixed-Signal Design.” Daniel Feldman, Vice President, Analog Mixed Signal Group Microsemi Corporation.	Microsemi
10:50 - 11:20	“The case for developing Custom Mixed-Signal SoCs.” Dermot Barry, Vice President Silicon, S3 Group.	S3 Group Dublin
11:20 – 12:00 Keynote	Keynote: “A New Paradigm: Disruptive SoC Design & Market Strategies.” Jim Aralis, Chief Technology Officer (CTO), and Vice President of R&D.	Microsemi
12:00 pm - 1:00 pm	Lunch
	Packaging Technologies, Trends & Challenges Track Chairman: Dr. Reza Ghaffarian, Jet Propulsion Laboratory, California Institute of Technology.
1:00 - 2:00 Panel	Panel: "3-D ICs . . . Technologies, Trends, Possibilities, and Challenges." Moderator: Dr. Sherie Motakef, Savant Company Inc., CTO, SoC Conference Organizing Committee. Panelists: 1. Lenny Reeves, Design Manager, Microsemi Corporation. 2. Dr. Norman Chang, VP and Sr. Product Strategist, Apache Design, subsidiary of Ansys, Inc. 3. Dr. Stephen Pateras, Product Marketing Director, Silicon Test, Mentor Graphics. 4. Joe Jeddeloh, Director of the Vendor's Advanced Storage Technology Center, Micron Technology, Inc. 5. Dr. Sang-Yun Lee, Founder, President, & CEO, BeSang Inc. 6. TBD.	SoC Conference Microsemi Apache Design Ansys Mentor Graphics Micron BeSang Inc.
2:00 - 2:40 Keynote	Keynote: “FPGA Packaging Trend and System Approach for Reliability.” Dr. Reza Ghaffarian, Jet Propulsion Laboratory, California Institute of Technology.	Jet Propulsion Laboratory & California Institute of Technology
2:40 - 2:50	Afternoon Break
	Emerging Memories: Technologies, Trends & Challenges Track Chairman: Dr. Muhammad M Khellah, Research Scientist at Intel Labs.
2:50 – 3:30 Keynote	Keynote: "Making Memristors a Reality: advances in physical understanding and device integration.” Dr. Janice H. Nickel, Ph.D., Cognitive Systems Laboratory, Hewlett-Packard Laboratories.	Hewlett Packard Laboratories
3:30 – 4:00	“Scaling Trends for Dense on Die Memory Arrays.” Dr. Muhammad M Khellah, Research Scientist at Intel Labs.	Intel
4:00 – 4:30	“NAND Flash Memory Technology Trends and Challenges." Dr. Yan Li, Sr. Director Memory Design & Advanced NAND Flash Memory Development, SanDisk.	SanDisk
4:30 – 5:00	"Integrated MEMS Resonators: High-precision Clock Source for SoCs." Dr. Sudhakar Pamarti, Associate Professor, University of California, Los Angeles.	UCLA & SiTime Corporation
3:00 pm - 8:00 pm Exhibit Reception & Job Fair	Conference Tabletop Exhibit & Reception Open -- Crystal Ballrooms A & B (Free Exhibit Pass, Many Door Prizes, etc.) Including IEEE-OC Student Design Contest IEEE Tech Job Fair (Catalina Ballroom)

Day TWO Oct 25, 2012 - SoC Conference Program Agenda*


Day Two Thursday October 25	Session	Company or University
7:00 am – 7:00 pm	Registration Open All Day Several Opportunities to Win various Prizes Throughout the Conference Program . . . Don't Miss Out!
8:00 - 8:10	"Welcome, Opening Remarks, and Conference Updates." Farhad Mafie, SoC Conference Chairman, IEEE OC SSCS & OCEN Chairs.	SoC Conference
	Emerging Technologies, Trends, and Possibilities in Designing Multicore Smart SoC Platforms. Track Chairman: Professor Masatoshi Ishikawa, University of Tokyo, Japan.
8:10 – 8:40	“Virtualization-Ready SoC: Challenges for Heterogeneous Multicore Architectures.” Dr. Florentine DUBOIS & Marcello Coppola, R&D Director at STMicroelectronics.	STMicro France
8:40 – 9:10	“SoC Performance and Performance/Watt Optimization” Maurice Steinman, an AMD fellow; Alexander Branover, principal staff.	AMD
9:10 – 9:40	Steve Cox, VP, Target Compiler Technologies.	Target Compiler Technologies
9:40 – 10:10	“High Speed Image Processing and Its Application Systems.” Professor Masatoshi Ishikawa, University of Tokyo, Japan.	University of Tokyo Japan
10:10 - 10:20	Morning Break
10:20 – 11:00 Keynote	Keynote: “Terahertz and Millimeter-Wave Imaging: New Frontiers of Electronics.” Payam Heydari, Professor, Nanoscale Communication Integrated Circuits (NCIC) Labs, Dept. of EECS, University of California, Irvine.	University of California, Irvine (UCI)
11:00 - 12:00 Panel	Panel: “Emerging Technologies, Trends, and Possibilities in Designing Multicore SoC Platforms." Moderator: Robert Cravotta, Principal Analyst at Embedded Insights Inc. Panelists: 1. Steve Cox, Vice President, Target Compiler Technologies. 2. Dr. Shireesh Verma, Pre-Silicon Validation Lead, Intel. 3. Wayne Locke, Director of ASIC Engineering, GigOptix. 4. Tom Ambrose, Sr. Director Engineering, Architecture, Emulex. 5. Dr. Philip Brisk, Assistant Professor, Department of Computer Science and Engineering, UC Riverside. 6. Thomas L. Anderson, Vice President, Marketing, Breker Verification Systems.	Target Compiler Technologies Embedded Insights GigOptix Inc. Breker Verification Systems Emulex UC Riverside Savant Company Inc.
12:00 – 1:00	Lunch
	FPGAs & SoCs: Trends, Security, Reliability & Verification in Designing Complex SoC Platforms. Track Chairman: Professor, Nader Bagherzadeh, University of California, Irvine (UCI), EECS.
1:00 – 1:40 Keynote	Keynote: "FPGAs and the Era of Silicon Convergence." Dr. Mike Peng Li, Fellow, Altera Corporation.	Altera
1:40 – 2:10	“Recent advances in the security of FPGA and cSoC devices.” Dr. Richard Newell, Senior Principal Product Architect, SoC Products Group, Microsemi Corporation.	Microsemi
2:10 – 2:40	“SoC Verification from the Inside Out.” Thomas L. Anderson, Vice President, Marketing, Breker Verification Systems.	Breker Verification Systems
2:40 – 3:10	“Design of Robust and Reliable Routing Algorithms for Network-on-Chip Architectures.” Professor, Nader Bagherzadeh, UCI, EECS.	University of California, Irvine (UCI)
3:10 – 3:20	Afternoon Break
3:20 – 3:50	“SoC Reliability and Quality." Austin Lesea, Xilinx Corporation.	Xilinx
3:50 – 4:20	“A Methodology to Verify SoC Straps, Parameter Settings and Register Resets” Thinh Ngo, Design Verification Engineer; Jain Sakar, Senior Verification Engineer; Randy Pascarella, Senior Design Engineer. Freescale Semiconductor, Inc.	Freescale Semiconductor, Inc.
4:20 – 4:30	Afternoon Break
4:30 – 5:30 Panel "FREE"	Panel: “Technology & Entrepreneurship: Dreams, Realities & Opportunities.” Moderator: Farhad Mafie, SoC Conference Chairman, IEEE OC SSCS & OCEN Chairs. Panelists: 1. Richard W. Henson, CEO, Source Scientific, LLC. 2. Eric Tanezaki, Intellectual Property Law Partner, Stetina Brunda Garred & Brucker. 3. Patrick Johnson, President & CEO, BioPhotas, Inc. 4. Susan Howington, CEO & Founder, Power Connections. 5. Dr. Goran Matijasevic, Executive Director of the Chief Executive Roundtable at the University of California, Irvine. This Panel Is Open To Everyone . . . Register Online for FREE Panel Pass More Updates Coming Soon . . . Several Opportunities to Win various Prizes During this Panel Discussion . . . Don't Miss Out!	Panel SoC Conference Source Scientific Stetina Brunda Garred & Brucker. BioPhotas, Inc. UCI Power Connections
5:30 – 6:30	Open To Everyone Reception & Networking	Savant Company Inc.
	10th International SoC Conference Closed.

* Program is subject to change. SoC Conference Organizing Committee, Technical Advisory Board (TAB), and Savant Company Inc. reserves the rights to revise or modify the SoC Conference program (the above program) at its sole discretion.

* * * * * * *

Back To The Main SoC Conference Page

Wafer images courtesy of Intel Corporation, Micron Technologies & Altera Corporation.