10th International SoC Conference

* Program is subject to change. SoC Conference Organizing Committee, Technical Advisory Board (TAB), and Savant Company Inc. reserves the rights to revise or modify the SoC Conference program at its sole discretion.


		Day One October 24, 2012 SoC Conference Program Agenda*
	Savant Company Inc.	Farhad Mafie, SoC Conference Chairman, IEEE OC SSCS & OCEN Chairs. Welcome and Opening Remarks, Technology/Market Trends. Farhad Mafie is SoC Conference Chairman. He has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience. He is the former Vice President of Marketing and Engineering at Toshiba Semiconductor. He has also worked in strategic marketing, project and design engineering at Lucent Technologies, Unisys, and MSI Data. Farhad has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton. He is an author and a translator, and his articles have been published in a variety of journals and Web-based magazines on technology and political affairs. In 2003, he published the biography of Iranian poet and Nobel nominee who lived in exile, Nader Naderpour (1929-2000), Iranian Poet, Thinker, Patriot. Farhad is also Editor-in-Chief for the CRC Press SoC Design and Technologies Book Series, which includes (1) Low-Power NoC for High-Performance SoC Design and (2) Design of Cost-Efficient Interconnect Processing Units. Farhad is an active member of IEEE, and he is the chair of IEEE Orange County Solid-State Circuits Society (SSCS), as well as IEEE Orange County Entrepreneurs' Network (OCEN). He is also a member of two UCI Advisory Committees: Communication System Engineering and Embedded System Engineering Certificate Programs.
		Analog and Mixed-Signal & SOI Design Trends and Challenges for Embedded Smart SoC Platforms Track Chairman: Dr. Janice H. Nickel, Ph.D., Cognitive Systems Laboratory, Hewlett-Packard Laboratories.
	IBM SOI Industry Consortium	Horacio Mendez, Executive Director, SOI Industry Consortium. Comparing SOI and Bulk Fully Depleted Devices such as FinFET and Planar CMOS. Abstract: The recent announcement of 3D transistors (FinFETs) in 22nm clearly points out to the technical superiority of Fully Depleted Transistors. The benefits of Fully Depleted Transistors have been recognized for some a long time, and are largely due to a much better sub-threshold slope and short channel effects. Fully Depleted transistors can be achieved through two basic approaches: planar Fully Depleted SOI (FD SOI) transistors or with 3D FinFETs. The technical advantage superiority of FD SOI was demonstrated earlier this year. Using an ARM M0 Cortex , FD SOI showed a frequency improvement of over 50% on a migration from 28nm Bulk (LP) to FD SOI at 0.9 volts. The results are even better more impressive at lower voltages. This presentation will focus on the key role that SOI will play in the formation of 2-dimmentional and 3-dimensional CMOS transistors and the excellent analog capabilities that SOI offers. Bio: TBA.
	Synopsys	Navraj S. Nandra, Senior Director Analog/Mixed-Signal IP Design Requirements For 28-nm and 20-nm Analog/Mixed-Signal IP Abstract: Power, performance and area (PPA) can be used as the metrics to define competitive analog/mixed-signal IP that is being integrated on today’s 28-nm SoC’s and in the early floor-planning phases for the next generation 20-nm platforms. These platforms are intended for tablets and smartphones making PPA the key considerations. The expectation is that IP’s such as data converters, physical interfaces for example USB, DDR and PCI Express, will follow the same shrink path as digital IP. This is not necessarily the case. In order to implement improvements in PPA, analog/mixed-signal IP may need to be re-designed to: 1) accommodate new design and density rules to support manufacturing; 2) meet aggressive PPA requirements in order to make the 20-nm platforms competitive. This presentation will describe the technical challenges and propose solutions for analog/mixed-signal IP on leading edge technology nodes. Bio: Navraj Nandra joined Synopsys in February 2005 and is the senior director of marketing for the DesignWare Analog and Mixed-signal IP products. He has worked in the semiconductor industry since the mid 80's as an analog/mixed signal IC designer for Philips Semiconductors, Austria Micro Systems, (San Jose & Austria) and EM-Marin (Switzerland). He has been responsible for the complete design of a number of analog front ends in application areas such as digital audio, RFID and automotive. Navraj holds a masters degree in Microelectronics, majoring in analog IC design, from Brunel University and a post-graduate diploma in Process Technology from Middlesex University. He has presented at numerous technical conferences on mixed-signal design, analog IP and analog synthesis/EDA.
	CEA-LETI France	Hughes Metras, VP, Strategic Partnerships, North America, CEA-LETI, France. Solutions for the future challenges of computing: low power CMOS FDSOI and Silicon photonics +3D Heterogeneous integration. Abstract: The computing industry is driven by two market segments. The low power applications ranging from mobile terminals to netbook through tablet PCs is becoming the leading field for the semiconductor industry while the HPC and Data warehouse field are calling for interconnect innovations due to the increasing number of switching nodes and memories at the system level. Leti is working on three key technologies that will have essential contributions to these issues: FDSOI is facing a bright future for the 28nm node and beyond thanks to its excellent merit factor in terms of power consumption and performance with a robust planar technology for industrialization. Silicon photonics on SOI is a platform that will offer low cost integration opportunities for advanced logic and memory chips to address switching nodes interconnection needs and memory access bandwidth limitations. The presentation will also highlight the importance of setting up new design environments with photonics and 3D models and libraries as well as testing tools and methodologies. Bio: Hughes Metras is VP in charge of Strategic Partnerships in North America for CEA-LETI, a major European R&D lab with 200 and 300 mm facilities in Grenoble France. He is also a visiting staff member at Caltech in the framework of the Alliance for Nanosystems VLSI where he is in charge of business development for the US region. Previously, Hughes was VP Marketing and Sales, in charge of business development and strategic planning. He coordinated Leti's sales and marketing teams in the field of semiconductors (advanced CMOS as well as heterogenous integration), imaging and photonics, biomedical technologies as well as telecommunications. Over the past two years, Mr. Metras has been involved in major French initiatives with key industrial players for the emergence of new programs in microelectronics addressing new societal challenges such as power conversion for industrial, automotive and PV applications. He has also been involved in the European technology platform EPOSS (smart system integration) where he coordinated the working group on key technologies and was a member of the executive committee.
	X-Fab	Paul Poenisch and Sebastian Schmidt. X-FAB. SOI technologies at X-FAB and their application space. Abstract: SoC designs have concentrated on increasing the integration of the high level functions of systems because those sections of the system usually constitute the majority of the components of the system. However modern portable appliances such as smart phones, tablet computers, GPS navigation systems, and MP3 players are adding more and more functions that are I/O intensive every year. These functions include orientation sensors, cameras, GPS, accelerometers, microphones, speakers, headphones, various radio frequency receivers and transmitters and many others. Each of these functions, as it is added, increases the number of components needed that are not high level digital components easily integrated into the main SoC device but often analog, power, or MEM devices that are not easily integrated into high density digital processes. The result is that the BOM for these systems tends to clime with time instead of benefiting from the intended reduction in BOM that SoC aims for. The solution to this problem is the analog and power equivalent of the digital SoC, ICs that can integrate a variety of analog, power, and other functions into a single die. However, accomplishing this integration is easier said than done. Until recently processes that could accomplish integrations of these types of functions were not economical. That is now changing as mixed-signal processes developed with smart functional integration are introduced. Bio: Paul Poenisch is an electrical engineer working in the applications group within the marketing department of X-Fab. His research work focused on modeling of photolithograph processes. He has been in the semiconductor industry for over 32 years working on process and device development for about 25 of those years then switching to the process application area. In that role he works with customers to optimize the application of X-Fab processes to their products.
	Morning Break	Morning Break
	Microsemi	Daniel Feldman, Vice President, Analog Mixed Signal Group Microsemi Corporation. Trends in Analog and Mixed-Signal Design. Abstract: TBD. Bio: Daniel Feldman is the Vice President of Sales for Microsemi’s Analog and Mixed-Signal Group and a member of the HDBaseT Alliance PoH technical committee. He is a former chairperson of the Ethernet Alliance PoE Technical Committee and was an active member of the IEEE802.3at Task Force. Previously, Mr. Feldman worked at Microsemi in several Business Development and Marketing roles, for PowerDsine as Senior Product Manager responsible for Outbound Marketing activities in the Americas, at IC4IC as System Architecture Group Manager, as a VHDL Engineer at NICE Systems and as VLSI Engineer at RAFAEL. Mr. Feldman holds an MBA from UC Berkeley’s Haas School of Business and a B.Sc. (Cum Laude) in Computer Engineering from the Technion Institute of Technology in Haifa, Israel.
	S3 Group	Dermot Barry, Vice President Silicon, S3 Group. The case for developing Custom Mixed-Signal SoCs. Abstract: Historically, the focus in the semiconductor industry was always how quickly you could move to the next geometry node. Now the question is how to make money by sustaining a specific node.” iSuppli (Len Jelinek ) Therein lies an opportunity for systems houses and OEMs, to develop custom mixed-signal SoC solutions for applications that just 3 to 4 years ago could not have justified the NRE to design, test and develop a complete product. An insatiable need for higher levels of integration of mainly digital SoCs, in high volume consumer applications (smartphones, tablets) has forced these applications to the most advanced process nodes (28nm ramping in 2012), and in doing so has freed up capacity in what are now mature process nodes (0.18µm to 90nm). In an effort to maintain fab utilization, manufacturers have lowered mask costs, in some instances quite drastically. There is clearly an opportunity for OEMs that traditionally couldn’t have justified development NRE, to now do so targeting process nodes at 90nm and older. In parallel, firms that develop and license Mixed Signal Intellectual Property (MSIP) now offer a growing portfolio of silicon proven MSIP in these mature processes. This further reduces the development time and cost, and more importantly risk for OEMs. This paper presents a case study from S3 Group, which makes the case for custom mixed signal SoC developments for applications for which sales volumes start at 50K+ units per annum. We will show how S3 Group was able to reduce the Bill of Material (BOM) cost for an OEM’s first generation product by greater than 50% by integrating the functionality of a number of standard ASSPs and discrete components into a two chip solution. While BOM cost reduction was the primary goal, other benefits included an increase in product reliability, a decrease in the product size, a vastly improved position in terms of security of supply and a design that can be used as the basis for further enhancements in the future. Bio: Dermot Barry has served as S3 Group's Vice President of the Silicon Business Unit since January 2006. Dermot's role involves setting the strategic direction for S3 Group's System-on-Chip (SoC) design services business and the Mixed Signal IP product portfolio. Dermot has full responsibility for global sales and operations and manages key strategic relationships, delivering successful solutions to OEM and Semiconductor clients in North America, Europe and Asia. In the period 2000 to 2005 Dermot was General Manager of the Wireless Systems Business Unit at S3 Group. Prior to re-joining S3 Group Dermot worked with Cadence Design Systems, from 1997-2000, as a Senior Sales Manager for Design Services in UK and Israel, again broadening his expertise and experience in the industry. Dermot first joined S3 Group in 1994 where he served in various Sales & Business Development roles, rising to become Vice President of US Sales & Business Development at S3 Group where he drove S3 Group's initial ventures into the North American marketplace while based in San Jose. Dermot started his career as a Research & Development Engineer for Philips Research in Eindhoven, The Netherlands, from 1985-1994 where he was responsible for analogue IC design focusing on ICs for mobile, broadcast and cordless communications. He currently serves on the Executive Committee of MIDAS Ireland and on the Design Advisory Board of the NMI UK. Dermot graduated from University College Dublin in 1985 with a 1st Class Honors Degree in Electronic Engineering.
	Microsemi Keynote	Jim Aralis, Chief Technology Officer (CTO), and Vice President of R&D. Keynote: "A New Paradigm: Disruptive SoC Design & Market Strategies." Jim Aralis has served as chief technology officer and vice president of R&D for Microsemi since January 2007. He has more than 30 years experience in developing custom analog device and process technologies, analog and mixed-signal ICs and systems, and CAD systems. Jim played a key role in transitioning Microsemi to a virtually fabless model, supporting multiple process technologies including, high voltage and high power BCD/CMOS, high power high integration CMOS, GaAs, SiGe, IPD, RF CMOS SoI, GaN, SiC, and several high-density packaging technologies. From 2000 to 2007, Jim established and served as senior design director of Maxim Integrated Product’s engineering center in Irvine, Calif. Before that, he spent 7 years with Texas Instruments/ Silicon Systems as mixed-signal design head and senior principal engineer. Additional experience includes 11 years with Hughes Aircraft Company in positions of increasing responsibility including senior scientist. Jim earned a bachelor of science degree in Math Applied Science and Physics and a master of science in electrical engineering from UCLA. He holds 9 patents for circuit and system design.
	Panel	Panel: "3-D ICs . . . Technologies, Trends, Possibilities, and Challenges."
	Panel Microsemi Apache Design Ansys Mentor Graphics Micron BEEcube Inc. BeSang Inc.	Dr. Sherie Motakef, Savant Company Inc., CTO, SoC Conference Organizing Committee. Moderator Bio: Dr. Sherie Motakef holds bachelor’s, master’s and doctorate degrees in Materials Sciences and Engineering and Optics from MIT and the University of Arizona. To complement her technical background, Dr. Motakef has over 15 years of experience in new business development, strategic and tactical marketing, and development of new applications in the semiconductors, chemicals, photonics, telecommunications, and defense industries. She has held various management roles at companies such as Air Products and Chemicals, Cymer, FEI, CVI Melles Griot, and BAE Systems. In her most recent role, she was the general manager of the Advanced Ceramics division of BAE Systems. Dr. Motakef is the author/co-author of multiple technical papers in peer-reviewed journals, she holds 1 US patent, and she is the recipient of awards from the American Chemical Society and the American Ceramic Society. Panelists: 1. Lenny Reeves, Design Manager, Microsemi Corporation. 2. Dr. Norman Chang, VP and Sr. Product Strategist, Apache Design, subsidiary of Ansys, Inc. 3. Dr. Stephen Pateras, Product Marketing Director, Silicon Test, Mentor Graphics. 4. Joe Jeddeloh, Director of the Vendor's Advanced Storage Technology Center, Micron Technology, Inc. 5. Dr. Sang-Yun Lee, Founder, President, & CEO, BeSang Inc. 6. TBD.
	Panelist BeSang Inc.	Dr. Sang-Yun Lee, Founder, President, & CEO, BeSang Inc. Panelist Bio: Dr. Lee is CEO of BeSang Inc., a fabless IP company is located in Beaverton, Oregon. A member of GSA since 2007, BeSang Inc. is a pioneer in 3D IC with nano-scale 3D integration and unrestricted 3D interconnections for the next generation of 3D IC. Dr. Lee has 23 years of industry and graduate research experience focused on semiconductor devices and process integration. He holds M.S. and Ph.D. degrees in Electrical Engineering from Washington University in St. Louis, MO and Arizona State University in Tempe, AZ, respectively. Before founding BeSang, he held various positions at Samsung, Motorola, and Integrated Device Technology.
	Panelist Mentor Graphics	Dr. Stephen Pateras, Product Marketing Director, Silicon Test, Mentor Graphics. Panelist Bio: Stephen Pateras is product marketing director within Mentor Graphics Silicon Test Solutions group and has responsibility for the company’s ATPG and DFT products. His previous position was VP Marketing at LogicVision where he was instrumental in defining and bringing to market several generations of LogicVision’s semiconductor test products. From 1991 to 1995, Stephen held various engineering lead positions within IBM’s mainframe test group. He received his Ph.D. in Electrical Engineering from McGill University in Montreal, Canada.
	Panelist Microsemi	Lenny Reeves, Design Manager, Microsemi Corporation. Panelist Bio: Lenny Reeves joined Microsemi in January 1981. He has more than 30 years of experience in microelectronic packaging, with an emphasis on multi chip module packaging and manufacturing. He has supported the design and development of stacked multi-chip module packages and the processes required to support the technologies in digital, analog and RF system design. He holds several US patents in the microelectronics packaging field.
	Panelist Micron Technology	Joe Jeddeloh, Director, Controller Development, Micron Technology. Panelist Bio: Joe Jeddeloh is Director of Controller Development, DRAM Solutions, at Micron Technology. Mr. Jeddeloh has worked for Micron for the past 17 years. He is named on over 200 patents in the areas of memory system architecture and controller development. His responsibilities include the management of the Minneapolis Design Center. His team is involved with the development of Micron’s Hybrid Memory Cubes (HMC), PCIe SSD controllers and DRAM testers. Mr. Jeddeloh holds a Bachelor of Science degree in electrical engineering from the University of Minnesota.
	Panelist Ansys, Inc. Apache Design	Dr. Norman Chang, VP and Sr. Product Strategist, Apache Design, subsidiary of Ansys, Inc. Panelist Bio: Norman Chang co-founded Apache Design Solutions in February 2001 and currently serve as VP and Sr. Product Strategist at Apache Design, a subsidiary of Ansys, Inc. Before co-founding Apache, Dr. Chang worked at Palo Alto HP Labs, leading a group focusing on interconnect related signal/power integrity issues and contributing to the HP-Intel IA64 micro-processor design. In 2000, he co-authored a widely read book on state-of-the-art methods for IC interconnect titled "Interconnect Analysis and Synthesis", published by John Wiley & Sons. He has twelve patents, and published more than 45 technical papers in journals and conferences. Dr. Chang receives his BS, MS, and Ph.D. in Electrical Engineering and Computer Sciences from University of California, Berkeley respectively at 1985, 1987, and 1990. He is currently a committee member for ESDA-EDA and Si2 Open3D workgroups.
	Lunch	Lunch
		Packaging Technologies, Trends & Challenges Track Chairman: Dr. Reza Ghaffarian, Jet Propulsion Laboratory, California Institute of Technology.
	JPL Keynote	Dr. Reza Ghaffarian, Jet Propulsion Laboratory, California Institute of Technology. Keynote: "FPGA Packaging Trend and System Approach for Reliability." Bio: Dr. Reza Ghaffarian has more than 30 years of industrial and academic experience. For the last 19 years at NASA/JPL, he led R&D reliability and quality assurance activities in advanced electronic packaging and has been a consultant resource for most JPL projects including Mars Curiosity Rover. He received many award including the NASA Exception Service Medal for outstanding leadership and industrial partnership. He has authored more than 150 technical papers, co-editor of a CSP book, 7 book chapters, and two guidelines. He serves as technical Advisor/Committee to IPC, Microelectronics Journal, SMTA, IMAPS and IEEE IEMT/CPMT. He received his Ph.D. in 1982 from University of California at Los Angeles (UCLA). Abstract: Commercial-off-the-shelf column grid array packaging (COTS CGA) technologies in high reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. This presentation reviews technology of IC packaging developed to meet demands of high processing powers, which come in area array packages. It then provides a more detail discussion on using field programmable gate array (FPGA), which enable programmer to modify software on-the-spot during product use. The FPGAs come in area array packages now have more than thousand solder balls/columns under package area not only need to be correctly joined onto PCB; they also should show adequate system reliability meeting thermo-mechanical requirements for application. In addition, recent FPGA packages not only come with flip-chip with underfill exposed, they have decoupling capacitors on the package substrates that further added complexity. The key packaging trends and system reliability approaches with test data will be also presented.
	Afternoon Break	Afternoon Break
		Emerging Memories: Technologies, Trends & Challenges Track Chairman: Dr. Muhammad M Khellah, Research Scientist at Intel Labs.
	HP Keynote	Dr. Janice H. Nickel, Ph.D., Cognitive Systems Laboratory, Hewlett-Packard Laboratories. Keynote: “Making Memristors a Reality: Advances in Physical Understanding and Device Integration.” Abstract: Memristors are the fourth fundamental circuit element which was predicted in the early 1970’s and reduced to practice in 2008. Unlike capacitors or inductors, memristors do not store charge or energy, but do store information. This quality makes them a candidate for next generation memory technology, potentially replacing Flash and DRAM, whose ability to scale to future technology nodes is limited by the fact that they rely on stored charge. Because of the ability to create highly non-linear memristive devices, this technology is feasible for true crossbar memories –without requiring select transistors. This will not only permit highly dense, stackable memory, it also will enable integration of memristive memory with compute processors. In this talk I will define memristive systems, describe their electrical properties and how they differ from the three other fundamental passive circuit elements. I will highlight properties of memristive devices, including switching speed, switching energy and analogue operation. Advances in fabricating memristors in fully CMOS compatible materials and processes, as well as results from integrated CMOS + memristor crossbar structures from the SK Hynix – HP Joint Development will be presented. Possible future applications of the technology will be discussed. TBD Bio: Dr. Janice Nickel is a Research Manager in the Cognitive Systems Laboratory at Hewlett-Packard Laboratories. She obtained her BA in Physics, and PhD in Materials Science and Engineering, from the University of California at Berkeley, and has nearly 20 years industrial experience inventing, developing and transferring innovative products for a DOW 30 company. She is currently leading the memristor productization effort. In this capacity, she is directing HP’s participation in the joint development of the technology with SK Hynix, as well as creating proprietary CMOS compatible memristor fabrication processes. This effort leverages a her previous experience in the development of MRAM crossbar memory technologies. Prior to working on memristors, Dr. Nickel invented a unique programmable drug delivery platform – “Smart Drug Delivery” – which repurposes HP’s mature ink jet technology to address unmet pharmaceutical market needs. She catalyzed multiple business units in disparate geographic locations to develop component modules which she integrated into a proof-of-concept demonstrator. She created a business plan, attracted investors, and transferred the technology to the startup Janisys, Ltd. The Smart Drug Delivery technology won the 2007 Silicon Valley Business Journal’s Emerging Technology Award in Medical Devices, and was recognized in Popular Science’s “Best of 2008” in the Health category. Janisys is currently developing the technology in partnership with a major pharmaceutical company. Dr. Nickel has 45 U.S. Patents awarded, over 40 scientific papers published, and numerous invited presentations.
	Intel	Dr. Muhammad M Khellah, Research Scientist at Intel Labs. Scaling Trends for Dense on Die Memory Arrays. Abstract: In this talk, we will go over scaling trends of dense embedded memory arrays in 22nm and beyond. Starting with conventional 6T SRAM, scaling continues with read and write assist schemes at the expense of extra design complexity, energy, and area. We will also address large array designs based on 8T cell, eDRAM 1T1C cell, and STT 1T1R cell. These technologies are increasingly becoming important alternatives to 6T SRAM that are predicted to continue the scaling of on die memories. Bio: Muhammad Khellah is a Research Scientist at Intel Labs, where he works on novel circuits and architectures focused on future low power microprocessor designs. After obtaining his PhD from the University of Waterloo Canada in 1999, he joined Intel and was involved in the design of SRAM caches for the Pentium microprocessor products. He has published over 70 technical papers in refereed international conferences and journals. He also has 55 patents granted, and 20 pending in the VLSI design area. Dr. Khellah currently serves as an associate editor for TCAS-I and is on the technical program committees of the ISLPED and the CICC.
	SanDisk	Dr. Yan Li, Sr. Director Memory Design & Advanced NAND Flash Memory Development, SanDisk. NAND Flash Memory Technology Trends and Challenges. Bio: Yan Li received B.S. degree from University of Science and Technology of China. She received M.S. and Ph.D. from Lehigh University in Pennsylvania. In 1998, she joined SanDisk Corporation, Sunnyvale, CA. She has been working on the circuit design of NAND flash memory since 2000. She led the team to design the industry first 3 bits per cell NAND memory and put it into production. She is currently a senior director for memory design and leading the advanced NAND flash memory development.
	SiTime Corporation &	Dr. Sudhakar Pamarti, Associate Professor, University of California, Los Angeles. Abstract: Timing references provide the heart beat of electronic systems. The electronics industry has historically relied on quartz-based timing components. Until recently timing devices have remained as stand-alone components since SoC designers and semiconductor manufacturers have never been able to integrate quartz-based timing. Over the past decade MEMS technology has become omnipresent in electronics and has since migrated to timing components. MEMS resonators can be a high-precision clock source for a SoC. Now available in die form, ultra-low-power zero-footprint MEMS resonators can be cost-effectively integrated into standard semiconductor packaging, replacing bulky external quartz devices. For SoC designers, MEMS resonators bring enhanced performance and new functionality providing time keeping (e.g. real-time clocks) and power management (e.g. sleep or wake-up). At the system level, integrated MEMS resonators improve system performance, reliability and resilience, power consumption and costs. Bio: Dr. Sudhakar Pamarti is an associate professor of electrical engineering at the University of California, Los Angeles. He received a Bachelor of Technology degree in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur in 1995, and M.S. and Ph.D. degrees in electrical engineering from the University of California, San Diego in 1999 and 2003, respectively. Prior to joining UCLA, he worked at Rambus Inc. (2003-2005) and Hughes Software Systems (1995-1997) developing high-speed I/O circuits and embedded software and firmware for a wireless-in-local-loop communication system respectively. Dr. Pamarti is a recipient of the National Science Foundation’s CAREER award for developing digital signal conditioning techniques to improve analog, mixed-signal, and radio frequency integrated circuits.
		Day TWO October 25, 2012 SoC Conference Program Agenda*
	Savant Company Inc.	Farhad Mafie, SoC Conference Chairman, IEEE OC SSCS & OCEN Chairs. Bio: Farhad Mafie is SoC Conference Chairman. He has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience. He is the former Vice President of Marketing and Engineering at Toshiba Semiconductor. He has also worked in strategic marketing, project and design engineering at Lucent Technologies, Unisys, and MSI Data. Farhad has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton. He is an author and a translator, and his articles have been published in a variety of journals and Web-based magazines on technology and political affairs. In 2003, he published the biography of Iranian poet and Nobel nominee who lived in exile, Nader Naderpour (1929-2000), Iranian Poet, Thinker, Patriot. Farhad is also Editor-in-Chief for the CRC Press SoC Design and Technologies Book Series, which includes (1) Low-Power NoC for High-Performance SoC Design and (2) Design of Cost-Efficient Interconnect Processing Units. Farhad is an active member of IEEE, and he is the chair of IEEE Orange County Solid-State Circuits Society (SSCS), as well as IEEE Orange County Entrepreneurs' Network (OCEN). He is also a member of two UCI Advisory Committees: Communication System Engineering and Embedded System Engineering Certificate Programs.
		Emerging Technologies, Trends, and Possibilities in Designing Multicore Smart SoC Platforms. Track Chairman: Professor Masatoshi Ishikawa, University of Tokyo, Japan.
	AMD	Maurice Steinman, an AMD fellow; Alexander Branover, principal staff. SoC Performance and Performance/Watt Optimization. Abstract: CPU and GPU on-die interaction and system memory sharing introduces non-trivial dependencies that have an impact on system-on-a-chip (SOC) performance and power. Software control over on-die components focuses mostly on each computing element, does not address an SOC in its entirety, and has an inherent inertia affecting the performance per watt. The ability to dynamically identify the CPU-centric or GPU-centric activity and promptly optimize the operational point and per-component power budget is a key factor in maximizing the performance and performance/watt of the heterogeneous CPU + GPU SOC. An on-die power management controller (PMC) dynamically allocates power to the compute unit (CU) that needs more power. This allows for CU performance improvement and faster task completion. Additionally, to exchange power credits between CUs, the PMC allocates power from other SOC components (memory PHY, I/O engines, internal display, etc.) in scenarios when these components are idle or less active than the respective power level to which the cooling solution is designed. Dynamic power allocation among SOC components maximizes the performance of the CPU- and GPU-focused workloads, and optimizes the performance of load-balanced workloads (i.e., OpenCL) while maintaining the SOC power within the thermal-design power (TDP) envelope. Bio: Alexander Branover is an AMD principal staff member involved in SOC architecture and power management. His research interests include SOC architecture, design, power management, and I/O protocols. Branover has worked on processor and system projects for more than 18 years. He has an MS in computer engineering from Technion (Institute of Technology), Israel, and is a member of the Peripheral Component Interconnect Special Interest Group (PCI-SIG). Bio: Maurice Steinman is an AMD fellow involved in NorthBridge and SOC architecture and power management. His research interests include client and server SOC architecture, design, and power management. Steinman has worked on processor and system projects for more than 25 years. He has a BS in computer and systems engineering from Rensselaer Polytechnic Institute and is a member of the Peripheral Component Interconnect Special Interest Group (PCI-SIG).
	STMicroelectronics	Dr. Florentine DUBOIS & Marcello Coppola, R&D Director at STMicroelectronics. Virtualization-Ready SoC: Challenges for Heterogeneous Multicore Architectures. Abstract: Nowadays consumer and mobile devices are pervasive in our everyday live and the application complexity is increasing exponentially. System-on-Chips for such devices are heterogeneous multi-core processors with specific hardware accelerators in which the performance/watt ratio is key selling and differentiation point. The required SoC flexibility is promoting an application-centric model, which faces new challenges such as openness (total decoupling from hardware to application software), security, programmability and performance. Virtualization, widely used in modern datacenter, allowing server consolidation, energy efficiency, green IT, business continuity, disaster recovery and data protection, could be also suitable to cope with some of the challenges faced by heterogeneous multi-core embedded systems. In this presentation, first a virtualization-ready SoC architecture addressing the aforementioned challenges will be presented. Next, we introduce the hardware virtualization by focusing not only on the well-known processor virtualization but on the hardware assisted virtualization for the overall SoC. Finally, some real scenarios in which virtualization could bring an added value are presented. Bio: Florentine Dubois received a Master degree in Computer Science from Institut National Polytechnique de Grenoble, in 2009. She then worked at TIMA laboratory (Grenoble) on routing in 3D Network-on-Chips before beginning in 2010 a PhD in collaboration with the same laboratory and STMicroelectronics. Her research interests are mainly focused on routing in irregular topologies and on the development of high-level performance estimation methods for Networks-on-Chips. Bio: Marcello Coppola graduated in Computer Science from the University of Pisa, Italy in 1992. He joined the Transputer architecture group in INMOS, Bristol (UK), doing research in multi-core communication together with the key technical people of Transputer technology with special focus in the C104 router. Later, he moved to the Advanced System Technology R&D group of STMicroelectronics, in which started and leaded different research programs. The last one, where he and his team developed the first industrial multiple-die Network-on-Chip called Spidergon STNoC, ended with the deployment company-wide of the technology and first integration in different 32nm multimedia and mobile SoCs. Currently, he is a Director in Home Entertainment & Displays Group, of STMicroelectronics, in Grenoble (France). His research interests include several aspects of design technologies for System-on-Chip, with particular emphasis to modeling, verification, network-on-chip, multi-core architecture and programming models. He's co-author and/or co-editor of different books and of over 50 technical articles. He is serving or has served as program and/or organizing member in numerous top international conferences and workshops. He has also served as reviewer for international conferences as well as journals and holds a number of patents.
	Target Compiler Technologies	Steve Cox, VP, Target Compiler Technologies - Maximizing Performance and Power Efficiency in Multicore Systems Abstract: SoCs with multicore architectures promise increased performance at reduce power. But, squeezing this performance out of such architectures has proven challenging, to put it mildly. The focus has turned toward software development, including tools, APIs, languages, and methodologies that promise to unlock all the inherent performance such multicore SoCs have to offer. Target’s MP Designer is a tool suite that enables iterative refinement of parallelization choices resulting in an implementation that is optimally balanced, providing the highest performance and lowest power. Bio: Steve Cox joined Target Compiler Technologies in 2006 and leads Target’s North American activities. Steve has a long history of innovation in the design and verification of processors and SoCs, including work at companies such as Accelchip, Apple, Ball Aerospace, Cadence, Cisco, Conexant, Intel, Motorola/Freescale, Nortel, and Solbourne Computer. Steve holds patents in the area of transaction-based verification of SoCs and is an alumnus of the University of Colorado. Steve currently resides in Boulder.
	University of Tokyo Japan	Professor Masatoshi Ishikawa, University of Tokyo, Japan. High Speed Image Processing and Its Application Systems. Abstract: Although conventional Image processing systems use video-rate for sampling images, video-rate is not sufficient for high-speed images of targets. Ishikawa et al. developed high-speed vision including general-purpose vision chips, target tracking vision chips column parallel intelligent vision systems, and reconfigurable embedded image processing systems. In addition, various types of application systems which open a new era of high-speed vision were developed. In my talk, basic architectures and implementations of high speed vision as well as its applications including human interface, robots, factory automation, visual inspection, bio-medical applications, vehicles, ITS, security, media, and interactive art are shown. Bio: Masatoshi Ishikawa received the B.E., M.E., and Dr. Eng. degrees in mathematical engineering and information physics from the University of Tokyo, Japan, in 1977, 1979, and 1988, respectively. From 1979 to 1989, he was a Senior Researcher at Industrial Products Research Institute, Tsukuba, Japan. From 1989 to 1999, he was an Associate Professor with the Department of Mathematical Engineering and Information Physics, University of Tokyo, where, from 1999 to 2001, he was a Professor. He was a vice-president and an executive vice-president of University of Tokyo, from 2004 to 2005, from 2005 to 2006, respectively. Since 2001, he has been a Professor of information physics and creative informatics at the University of Tokyo. His current research interests include robotics, sensor fusion, high speed vision, visual feedback, dynamic image control, and meta perception.
	UCI Keynote	Payam Heydari, Professor, Nanoscale Communication Integrated Circuits (NCIC) Labs, Dept. of EECS, University of California, Irvine. Terahertz and Millimeter-Wave Imaging: New Frontiers of Electronics. Abstract: This keynote speech gives comprehensive overview of Terahertz and millimeter-wave (including both active and passive) imaging and their enabling and exciting applications. The speech then reviews current efforts to push the design of integrated circuits to operate at millimeter-wave and Terahertz frequency range. The talk covers daunting challenges in designing Terahertz building blocks and active/passive imaging systems at various levels of design hierarchy including system- and architecture-level down to the circuit- and device-levels. Bio: Payam Heydari (S’98–M’00–SM’07) received the B.S. and M.S. degrees (with highest honors) in electrical engineering from the Sharif University of Technology in 1992 and 1995, respectively. He received the Ph.D. degree in electrical engineering from the University of Southern California in 2001. Dr. Heydari is currently a Full Professor of Electrical Engineering and also School of Engineering Faculty Vice Chair. His research interests include the design of high-speed analog, radio-frequency (RF), and mixed-signal integrated circuits. He is the (co)-author of one book and 100 journal and conference papers. The Office of Technology Alliances at UCI has named Dr. Heydari one of 10 outstanding innovators at the university. Dr. Heydari is the co-recipient of the 2009 Business Plan Competition First Place Prize Award and Best Concept Paper Award both from Paul Merage School of Business at UC-Irvine. He is the recipient of the 2010 Faculty of the Year Award from UC-Irvine's Engineering Student Council (ECS), the 2009 School of Engineering Fariborz Maseeh Best Faculty Research Award, the 2007 IEEE Circuits and Systems Society Guillemin-Cauer Award, the 2005 NSF CAREER Award, the 2005 IEEE Circuits and Systems Society Darlington Award, the 2005 UCI’s School of Engineering Teaching Excellence Award, the Best Paper Award at the 2000 IEEE International Conference on Computer Design (ICCD), the 2000 Honorable Award from the Department of EE-Systems at the University of Southern California, and the 2001 Technical Excellence Award in the area of Electrical Engineering from the Association of Professors and Scholars of Iranian Heritage (APSIH). He was recognized as the 2004 Outstanding Faculty at the UCI’s EECS Department. Dr. Heydari’s paper entitled: Design of Ultra High-Speed Low-Voltage CMOS CML buffers and Latches, published in October 2004 issue of the IEEE Trans. on VLSI Systems, was ranked first among top downloaded articles in 2007. His research on novel low-power multi-purpose multi-antenna RF front-ends received the Low-Power Design Contest Award at the 2008 IEEE Int'l Symposium on Low-Power Electronics and Design (ISLPED). He is the co-founder of ZeroWatt Technologies, Inc., a fabless semiconductor startup in low power mixed signal integrated circuits design. Dr. Heydari is a Guest Editor of IEEE Journal of Solid-State Circuits. He currently serves on the Technical Program Committees of Compound Semiconductor IC Symposium (CSICS) and International Symposium on Low-Power Electronics and Design (ISLPED). He was an Associate Editor of the IEEE Transactions on Circuits and Systems – part I from 2006 to 2008. He was a Technical Program Committee member of the IEEE Custom Integrated Circuits Conference (CICC), and International Symposium on Quality Electronic Design (ISQED).
	Panel	Panel: “Emerging Technologies, Trends, and Possibilities in Designing Multicore SoC Platforms."
	Panel 11:00 - 12:00 Target Compiler Technologies Embedded Insights GigOptix Inc. Breker Verification Systems Emulex UC Riverside Savant Company Inc.	Robert Cravotta is the principal analyst at Embedded Insights Inc, and Contributing Editor at EDN Magazine. Moderator Bio: Robert Cravotta is the principal analyst at Embedded Insights Inc. As a former Technical Editor covering Embedded Processing at EDN, Robert has been following and commenting on the embedded processing space since 2001. His expertise includes software development and system design using microprocessors, microcontrollers, digital signal processors (DSPs), multiprocessor architectures, processor fabrics, coprocessors, and accelerators, plus embedded cores in FPGAs, SOCs, and ASICs. Robert's embedded engineering background includes 16 years as a Member of the Technical Staff at Boeing and Rockwell International working on path-finding avionics, power and laser control systems, autonomous vehicles, and vision sensing systems. 1. Steve Cox, Vice President, Target Compiler Technologies. 2. Dr. Shireesh Verma, Pre-Silicon Validation Lead, Intel. 3. Wayne Locke, Director of ASIC Engineering, GigOptix. 4. Tom Ambrose, Sr. Director Engineering, Architecture, Emulex. 5. Dr. Philip Brisk, Assistant Professor, Department of Computer Science and Engineering, UC Riverside. 6. Thomas L. Anderson, Vice President, Marketing, Breker Verification Systems.
	UC Riverside	Dr. Philip Brisk, Assistant Professor, Department of Computer Science and Engineering, UC Riverside. Panelist. Bio: Philip Brisk received his B.S., M.S., and Ph.D. degrees, all in Computer Science, from UCLA in 2002, 2003, and 2006 respectively. From 2006-2009, he was a postdoctoral scholar in the Processor Architecture Laboratory at the Ecole Polytechnique Federale de Lausanne (EPFL) in Switzerland. Since 2009, he has been an Assistant Professor in the Department of Computer Science and Engineering at the University of California, Riverside. Dr. Brisk's research interests include embedded processor architecture and customization, FPGAs and reconfigurable computing, compilers, VLSI-CAD, computer arithmetic, and emerging microfluidic technologies. He has received best paper awards at CASES 2007 and FPL 2009, and has been nominated for best paper awards at DAC 2007 and HiPEAC 2010. He is a member of the ACM and IEEE.
	Panelist Target Compiler Technologies	Steve Cox, VP, Target Compiler Technologies. Panelist Bio: Steve Cox joined Target Compiler Technologies in 2006 and leads Target’s North American activities. Steve has a long history of innovation in the design and verification of processors and SoCs, including work at companies such as Accelchip, Apple, Ball Aerospace, Cadence, Cisco, Conexant, Intel, Motorola/Freescale, Nortel, and Solbourne Computer. Steve holds patents in the area of transaction-based verification of SoCs and is an alumnus of the University of Colorado. Steve currently resides in Boulder.
	Panelist Intel	Dr. Shireesh Verma, Pre-Silicon Validation Lead, Intel. Panelist Bio: Shireesh Verma is currently with Intel. Prior to that he has held research and development positions at Conexant, Qualcomm Inc. and Marvell Semiconductor Inc. He has been involved in extensive research on various aspects of verification like, automatic generation and evaluation of functional and syntactic coverage models, coverage feedback driven test generation, behavioral error models, low power verification techniques, etc for the past 9 years. He obtained his PhD degree in Information and Computer Science from the University of California Irvine. He has led several in-house Design and Verification tool development efforts during his industrial stints. He has published numerous conference papers, journal and magazine articles and a book chapter. He has also delivered numerous invited tutorials and has been invited at several panels in these areas. He serves on the editorial board of Journal of Low Power Electronics (JOLPE). He is also a member of the Accellera P1801 Low Power Working Group and the IEEE Design Automation Standards Committee. He is a member of the Technical Program Committees of "ACM/IEEE Design Automation and Test in Europe (DATE) Conference", "IEEE International High Level design Validation and Test (HLDVT) Workshop", and "International Symposium on Quality Electronic Design (ISQED)". He is also a member of the organizing committee (Publicity chair) of the HLDVT 2009.
	Breker Verification Systems	Thomas L. Anderson, Vice President, Marketing, Breker Verification Systems. Panelist Bio: Thomas L. Anderson is Vice President, Marketing at Breker Verification Systems in Mountain View, CA. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at 0-In Design Automation. Before moving into EDA he was Vice President of Engineering at IP pioneer Virtual Chips, following roles in ASIC design and management. Tom has presented more than 100 conference talks, published more than 150 papers and articles, and contributed to 12 books. He holds a BS in Computer Systems Engineering from the University of Massachusetts at Amherst and an MS in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology (MIT).
	Panelist Emulex	Tom Ambrose, Sr. Director Engineering, Architecture, Emulex. Panelist Bio: Tom Ambrose is Sr. Director of Engineering in the Systems, Technology, and Architecture Department at Emulex Corporation. He is responsible for defining ASIC architectures and product requirements for networking and storage products. He has 20 years of experience in ASIC design and management for products, including Ethernet and Fibre Channel adaptors and switches, and consumer printers. Mr. Ambrose holds a B.S. of Electrical and Computer Engineering from Carnegie Mellon University.
	Panelist GigOptix Inc.	Wayne Locke, Director of ASIC Engineering, GigOptix. Panelist Bio: Wayne has more than 25 years of experience in the semiconductor industry, primarily in ASIC design. He came to Gigoptix through the acquisition of the ChipX ASIC business in 2009. Wayne has held engineering management roles at Texas Instruments, VLSI Technology, and Prairiecomm prior to joining ChipX in 2004. Wayne earned BS and MS degrees in Electrical Engineering from Duke University.
	Lunch	Lunch
		FPGAs & SoCs: Trends, Security, Reliability & Verification in Designing Complex SoC Platforms. Track Chairman: Professor, Nader Bagherzadeh, University of California, Irvine (UCI), EECS.
	Altera Keynote	Dr. Mike Peng Li, Fellow, Altera Corporation. Keynote: "FPGAs and the Era of Silicon Convergence." Abstract: Customer demand and the economies of the industry are driving a trend towards “silicon convergence.” Each new silicon process node allows chip designers to put more components-processors, accelerators, memory, and peripheral controllers, high-speed I/Os and photonic ICs-onto a single chip. More components means more capability, higher performance, higher throughput, lower power, and less area and space which are in high demand by system designers developing tomorrow’s cutting edge technologies. 3D and photonic enabled SoC FPGAs are leading the way in this trend and delivering customizable functionality and hardware acceleration for wired and wireless communications, computing, storage, military, industrial and automotive applications. Bio: Dr. Li has been with Altera Corporation since Sept., 2007 and currently is an Altera Fellow. He is a corporate expert and adviser, as well as CTO office principal investigator, on high-speed link/standards, SERDES architecture, electrical and optical signaling, silicon photonics, optical FPGA, high-speed debug and test, jitter, noise, signal and power integrity. He was the Chief Technology Officer (CTO) for Wavecrest Corporation from 2000-2007. Dr. Li is a Fellow of IEEE, and an affiliated professor at the Department of Electrical Engineering, University of Washington, Seattle. He holds a Ph.D. in physics (1991), an M.S.E (1991), in electrical and computer engineering and an M.S. in physics (1987), from the University of Alabama, Huntsville. He also holds a B.S (1985) in space physics from the University of Science and Technology of China. He was a Post Dr. and then a research scientist at the University of California, Berkeley (1991-1995).
	Microsemi	Dr. Richard Newell, Senior Principal Product Architect, SoC Products Group, Microsemi Corporation. Recent advances in the security of FPGA and cSoC devices. Abstract: TBD. Bio: Richard Newell is Senior Principal Product Architect at Microsemi Corporation, SoC Products Group where he has been active in planning the security features for the next generation of Flash-based FPGAs and customizable System-on-Chips (cSoCs) as well as expanding the available solutions for Microsemi’s current device families. Richard has an electrical engineering background, with experience in analog and digital signal processing, cryptography, control systems, inertial sensors and systems, and FPGAs. He is an alumni of the University of Iowa. He is the recipient of approximately one dozen U.S. patents and is a member of the Tau Beta Pi and Eta Kappa Nu honorary engineering societies.
	Breker Verification Systems	Thomas L. Anderson, Vice President, Marketing, Breker Verification Systems. SoC Verification from the Inside Out. Abstract: There is a dangerous emerging trend in the system-on-chip (SoC) world: the assumption that well-verified IP blocks can be quickly assembled and shipped as a complete SoC. A team making this assumption may indeed be able to stitch the IP blocks together easily; modern fabric-based SoC platform architectures and chip-assembly tools work well. However, the team generally performs minimal full-chip verification, under this same assumption that thorough block-level verification is enough to “stitch and ship” the SoC. The truth is very different. Even IP blocks that are verified 100% standalone may behave very differently when stitched into the full SoC. The IP blocks must share a broad range of chip-level resources, such as memories, bus fabric, and multiple I/O channels. Two IP blocks that access memory fine on their own may conflict when connected together. The combined IP bandwidth requirements may overwhelm the bus fabric, requiring the insertion of wait states and diminished performance. Similarly, multiple IP blocks trying to access the same I/O channel may exceed its capacity. Why doesn’t the SoC verification team do a better job at the full-chip level? Of course, they are relying on the same incorrect assumption. Project management may make this assumption as well and allot little time in the schedule for full-SoC verification. Further, it is hard to develop a full-chip testbench that can stress the corner cases involving shared resources. This is verification “from the outside in” that takes no advantage of the powerful processors embedded within the SoC. Even if the verification team writes a few C tests to run on the embedded processors, these tests have no link to the testbench. This session presents a novel approach to verifying the SoC from the inside out, generating self-verifying C test cases that run on the embedded processors. For test cases that read or write data from the chip’s I/O channels, the test cases coordinate with appropriate testbench components. Since the real power of the SoC lies in its processors, leveraging them for verification makes it much easier to exercise corner-case conditions than working purely from an external testbench. The result is more thorough verification before tape-out and a higher likelihood of first-silicon success. Bio: Thomas L. Anderson is Vice President, Marketing at Breker Verification Systems in Mountain View, CA. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at 0-In Design Automation. Before moving into EDA he was Vice President of Engineering at IP pioneer Virtual Chips, following roles in ASIC design and management. Tom has presented more than 100 conference talks, published more than 150 papers and articles, and contributed to 12 books. He holds a BS in Computer Systems Engineering from the University of Massachusetts at Amherst and an MS in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology (MIT).
	UCI	Professor, Nader Bagherzadeh, UCI, EECS. Design of Robust and Reliable Routing Algorithms for Network-on-Chip Architectures. Abstract: Network-on-Chip (NoC) systems have been proposed to achieve high performance computing where multiple processors are integrated into one chip. As the number of cores increases and the chips are scaled in the deep submicron technology, NoC systems become subject to physical manufacture defects and running-time vulnerability, which result in faults. Faults affect the performance and functionality of the NoC systems and result in communication malfunctions. Nevertheless, NoC architectures have enough resources to tolerate faults by rerouting packets and remapping tasks. The rerouting algorithms may introduce new issues such as deadlock and livelock cases. In this presentation, we will discuss how to design routing algorithms that tolerate multiple faults and feature deadlock and livelock freedom. Bio: Dr. Nader Bagherzadeh has been involved in research and development in the areas of computer architecture, reconfigurable computing, VLSI chip design, and computer graphics. For almost ten years ago, he was the first researcher working on the VLSI design of a Very Long Instruction Word (VLIW) processor. Since then, he has been working on multithreaded superscalars and their application to signal processing and general purpose computing. His current project at UC, Irvine is concerned with the design of coarse grain reconfigurable pixel processors for video applications. The proposed architecture, called MorphoSys, is versatile enough to be used for digital signal processing tasks such as the ones encountered in wireless communications and sonar processing. DARPA and NSF fund the MorphoSys project (total support $1.5 million). Dr. Bagherzadeh was the Chair of Department of Electrical and Computer Engineering in the Henry Samueli School of Engineering at University of California, Irvine. Before joining UC, Irvine, from 1979 to 1984, he was a member of the technical staff (MTS) at AT&T Bell Laboratories, developing the hardware and software components of the next-generation digital switching systems (#5 ESS). Dr. Bagherzadeh holds a Ph.D. in computer engineering from The University of Texas at Austin. As a Professor, he has published more than a hundred articles in peer-reviewed journals and conference papers in areas such as advanced computer architecture, system software techniques, and high performance algorithms. He has trained hundreds of students who have assumed key positions in software and computer systems design companies in the past twelve years. He has been a Principal Investigator (PI) or Co-PI on more than $2.5 million worth of research grants for developing next-generation computer systems for solving computationally intensive applications related to signal and image processing.
	Afternoon Break	Afternoon Break
	Xilinx	Austin Lesea, Xilinx Corporation. SoC Reliability and Quality. Abstract: When considering a system-on-chip for your application, issues of quality, reliability, availability, and product longevity must be taken into account at the beginning of any project. Within the reliability category alone, there are many factors to be considered including software reliability, probability of soft and hard errors and the expected lifetime of the device once it's in the field. Additionally, the market served by the end-product will most often have its own requirements that may become hidden costs, or even risks, if not addressed upfront. For example, safety-critical standards for specific markets such as automotive, industrial and aerospace may have requirements that can lead to impossible-to-meet specifications for those who choose to fabricate their own devices. This talk will detail what you need to know to address safety-critical markets, and use Xilinx's example of providing the silicon, tools, development platforms, intellectual property (IP) along with the training and support to meet the needs of SoC-based systems using the Zynq-7000 All Programmable SoC, a programmable logic device with an integrated industry-standard dual ARM(r) Cortex(tm)-A9 MPCore(tm) subsystem. Bio: Austin Lesea (M’75) Austin received his Bachelor of Science in Electrical Engineering and Computer Sciences, University of California at Berkeley in 1975. In 1976 he received his Masters of Science in Electrical Engineering and Computer Sciences, University of California at Berkeley in optimization, control, and communications theory. He has spent the first year of his career teaching, and writing the book, Microprocessor Interfacing Techniques (1976, Sybex Publishing, Berkeley, California). He spent the next 13 years designing telecommunications transmission (copper, fiber optic, digital microwave), switching (PBX and ACD systems), and synchronization systems (building integrated timing systems). During that time, he spent eight years on the ATIS/ANSI T1 Committees helping write the SONET and TI CPE standards. Mr. Lesea then spent 11 years at Xilinx where as a Principal Engineer in the IC design group where he has been part of the design efforts for five product families. His last project was as the lead hardware architect and radiative effects designer for the Xilinx Q5 “rad-hard” by design FPGA device, now in use in orbital space applications (in orbit today, and chosen for many missions). He then joined Xilinx Research Labs where he been looking at soft error effects for the last four years. Recent interests also include encryption and security. At the time of this paper, he holds 66 patents.
	Freescale Semiconductor, Inc.	Thinh Ngo, Design Verification Engineer; Jain Sakar, Senior Verification Engineer; Randy Pascarella, Senior Design Engineer. Freescale Semiconductor, Inc. A Methodology to Verify SoC Straps, Parameter Settings and Register Resets. Abstract: SoC needs to correctly strap, or tie off, a set of built-time vectors for each supported product personality. For instance, a strap vector may be used to configure an embedded core 's personality (i.e. number of threads, cores, clusters). Likewise, build parameters are widely used to personalize RTL for each product personality. Thousands of parameters are used in each SOC to configure bus widths, FIFO depths, clock ratios, etc. Moreover, register reset values are product-dependent. They define product identification, version number, etc. Traditionally, strap and parameter settings are verified via design review and lint checking. Register reset values are verified via directed tests. It is apparent that these methods do not scale well. As SOC personalities proliferate, the set of build configuration vectors, parameters, and values multiplies and increases the risk of error. In this paper, we propose a universal methodology where immediate assertions are used to rigorously verify these settings. This methodology offers a number of advantages. Firstly, immediate assertions functionally verify these settings. Secondly, they efficiently execute once per test. Thirdly, they effectively verify every test; Fourthly, they are portable and re-useable since they can bind to hardware modules as VIPs. Finally, they are concise, easy to write and read, and as a result they can be readily scripted for extraction from design specifications and reporting from verification plans. Bio: TBD.
	Afternoon Break	Afternoon Break
	Panel (FREE for Everyone!)	“Technology & Entrepreneurship: Dreams, Realities & Opportunities” Open To Everyone
	Savant Company Inc. SoC Conference Source Scientific Stetina Brunda Garred & Brucker. UCI BioPhotas, Inc. Power Connections	Farhad Mafie, SoC Conference Chairman, IEEE OC SSCS & OCEN Chairs. Moderator Bio: Farhad Mafie is SoC Conference Chairman. He has over 20 years of experience in semiconductor and computer businesses and more than 10 years of university-level teaching experience. He is the former Vice President of Marketing and Engineering at Toshiba Semiconductor. He has also worked in strategic marketing, project and design engineering at Lucent Technologies, Unisys, and MSI Data. Farhad has a Master of Science and a Bachelor of Science degree in Electronic Engineering from California State University, Fullerton. He is an author and a translator, and his articles have been published in a variety of journals and Web-based magazines on technology and political affairs. In 2003, he published the biography of Iranian poet and Nobel nominee who lived in exile, Nader Naderpour (1929-2000), Iranian Poet, Thinker, Patriot. Farhad is also Editor-in-Chief for the CRC Press SoC Design and Technologies Book Series, which includes (1) Low-Power NoC for High-Performance SoC Design and (2) Design of Cost-Efficient Interconnect Processing Units. Farhad is an active member of IEEE, and he is the chair of IEEE Orange County Solid-State Circuits Society (SSCS), as well as IEEE Orange County Entrepreneurs' Network (OCEN). He is also a member of two UCI Advisory Committees: Communication System Engineering and Embedded System Engineering Certificate Programs. Panelists: 1. Richard W. Henson, CEO, Source Scientific, LLC. 2. Eric Tanezaki, Intellectual Property Law Partner, Stetina Brunda Garred & Brucker. 3. Patrick Johnson, President & CEO, BioPhotas, Inc. 4. Susan Howington, CEO & Founder, Power Connections. 5. Dr. Goran Matijasevic, Executive Director of the Chief Executive Roundtable at the University of California, Irvine. This Panel Is Open To Everyone . . . Register for FREE Panel Pass More Updates Coming Soon . . . Several Opportunities to Win various Prizes During this Panel Discussion . . . Don't Miss Out!
	Source Scientific.	Richard W. Henson, CEO, Source Scientific, LLC. Panelist Bio: Richard Henson is CEO and one of the founders of Source Scientific, LLC, a medical instrument and device development firm in Irvine, California. Here, he and his partners developed original technology used in diagnostics. Today, Source Scientific develops and manufactures products for many well-known in-vitro diagnostic, ophthalmic, surgical and medical device companies. An experienced CEO with public company experience, Richard has worked with many high-tech firms in biomedical, consumer and critical power industries. He has a strong combination of technical, sales, marketing and managerial experience. He spent several years in Europe with Swiss-based manufacturers of critical power equipment for heavy industrial markets including nuclear, power generation, oil & gas, petrochemical and transportation. He has also served as President of Clary Corporation, a public company that manufactures harsh environment power systems for medical, military and transportation applications. Mr. Henson also serves on the CEO Roundtable at UC Irvine and the Octane Board of Directors. He is an alumnus of the Anderson School of Business at UCLA. He also attended California State University, Long Beach (CSULB). He has 4 children and lives in Laguna Beach, California.
	Stetina Brunda Garred & Brucker	Eric Tanezaki, Intellectual Property Law Partner, Stetina Brunda Garred & Brucker. Panelist Bio: Eric is a partner of Stetina Brunda Garred & Brucker, a boutique full service intellectual property law firm. He has represented numerous companies in various industries in relation to patent, trademark and copyright matters, seeking rights as well as related licensing. He received his undergraduate engineering degree from the University of Southern California, and his law degree from the McGeorge School of Law, University of the Pacific. Prior to law school Eric worked in the aerospace industry. Eric is the Executive Director of the Southern California Venture Network (SCVN.org). In addition, Eric is the IP Law Mentor to the USC Stevens Institute for Innovation.
	University of California, Irvine	Dr. Goran Matijasevic, Executive Director of the Chief Executive Roundtable at the University of California, Irvine. Panelist Bio: Dr. Goran Matijasevic is Executive Director of the Chief Executive Roundtable at the University of California, Irvine. In that capacity, he oversees and advances research collaborations and strategic initiatives associated with Roundtable programs, protocol and mission objectives. He also serves as UC Irvine's ambassador to the local and national business community, establishing partnerships and opportunities that serve to enhance leader-to-leader connections across all campus interdisciplinary fields. Prior to this position, he was director of research development at The Henry Samueli School of Engineering at UC Irvine, as well as research coordinator of the Integrated Nanosystems Research Facility, where he worked on formation of new industry-university and academic collaborations, especially focusing on new interdisciplinary research initiatives. Prior to UCI, he worked as a senior engineer at QPlus, a telecommunications start-up company, and Director of Research and Ormet Technologies, a developer of electronic materials and technologies. He managed multiple SBIR projects that led to several industry consortia projects, as well as a license agreement with a Fortune 100 company. He has 4 U.S. patents, 3 book chapters, and over 40 conference and journal publications and has served on the NEMI Industry Roadmap committee. Goran is currently on the OCTANe (Orange County Technology Action Network) Biomedical Industry Leadership Council, the Board of Southern California Biomedical Council, and the advisory boards of 2-1-1 Orange County and TriTech SBDC. He is Vice President of the University Industry Demonstration Partnership (UIDP), a national organization working under the auspices of the National Academies. Goran received his PhD from UC Irvine in Electrical and Computer Engineering and his MBA from Pepperdine University. He may be reached at goran@uci.edu.
	Power Connections	Susan Howington, CEO & Founder, Power Connections. Panelist Bio: Susan Howington is a sought-after expert in the Executive Career Transition field, applying her practical knowledge and visionary wisdom as a consultant, coach, author and industry speaker. Her success derives from her understanding that in circumstances of executive outplacement, nothing replaces the effectiveness of human interaction and person to person connections. Through her company, Power Connections, Susan utilizes her highly respected reputation to assist companies in transitioning their executives during outplacement initiatives. Susan made her mark in the industry throughout her executive tenure with the firm of Lee Hecht Harrison, a global player in outplacement and executive coaching services. Under Susan’s leadership as Senior Vice President and Managing Director of the Southern California region, the company reached premier executive status in Orange County. Likewise, taking an active interest personally and professionally in the emerging coaching industry, Susan became Lee Hecht Harrison’s top achiever in sales of executive coaching and leadership development services. She received the 2003 Lee Hecht Harrison Global Leadership Consulting Award, participated as a member of the company’s Executive Strategic Planning Committee for 2005 and 2006; and attained membership in the company’s prestigious President’s Circle in 2004 and 2005. Susan’s entrée into the career transitions industry was as an Account Executive with Drake Beam Morin of Newport Beach. A natural networker, Susan increased the sales in her territory over 700% in her tenure there. Prior to entering the career transition industry, Susan performed the roles of Director of Buyer Services and Director of Business Development with The Geneva Companies, a mergers and acquisitions firm. Susan was awarded a leadership scholarship to attend the international Institute of Management Development (IMD) in Lausanne, Switzerland for two terms, 2005 and 2006. In Orange County, she was profiled by OC Metro Magazine as one of 15 Orange County Women Who Inspire Others. She has appeared in the Orange County Register, Los Angeles Times, national online publications like ABC7 New York, CBS2 Chicago, Fox Business News, and CareerBuilder.com to name a few. She is the author of the just released book on Amazon.com called “How Smart People Sabotage Their Job Search: 10 Mistakes Executives Make and How to Fix Them.” Susan served on the Orange County Board of the March of Dimes from 2004 to 2006; and as the Membership Chair of the National Human Resources Association (NHRA) in 2000. She served as 2008, 2009, 2011 Co-Chair for the National Human Resources Association HR Executive of the Year Award... She has been a member of Vistage (formerly TEC) since 2002, and the Marketing Executive Networking Group (MENG) since 2007. Susan earned a B.S. degree in Sociology with a minor in Psychology from Northern Arizona University.
	Power Connections	Patrick L. Johnson, President & Chief Executive Officer, BioPhotas, Inc. Panelist Bio: Patrick L. Johnson – President &Chief Executive Officer – BioPhotas, Inc. Mr. Johnson is a seasoned executive with P&L leadership in turnarounds, start-ups, emerging companies, as well as companies challenged with mature product life cycles. With a history of repeatedly growing sales and gross margins at double digit growth rates, Patrick has provided leadership in strategic planning, sales, marketing, corporate branding, product positioning, and operations. Patrick is a senior executive with 25 years experience leading manufacturing companies in diverse industries including medical, dental, aerospace, and motorsports. His recent leadership experience includes ten years with Pro-Dex, Inc., a publicly-held medical device manufacturer, serving in the roles of Chief Business Development Officer, CEO and President, and Board Member. Mr. Johnson left Pro-Dex in early 2010 to start-up a humanitarian relief organization, The WorldBed Project. The charter of this organization was to build strategic alliances with government, NGOs, corporations, and individuals to bring badly needed funding to Haiti in the aftermath of the earthquake. Prior to Pro-Dex, Mr. Johnson held senior management positions with Sybron Dental Specialties, Tycom Dental, and Dabico Inc. Patrick graduated from the University of California with Honors, earning Bachelors of Arts degrees in Philosophy and Legal Studies. Patrick also earned his Masters of Arts in Business Administration from Pepperdine University. Mr. Johnson currently serves as a Entrepreneur in Residence at Chapman University Leatherby Center for Entrepreneurship. Patrick is married, the father of three and grew up in the City of Orange, a 3rd Generation Orange Countian.
		Open To Everyone Reception & Networking
		10th International SoC Conference Closed.