The 18th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

 September 14 & 15, 2021

University of California, Irvine (UCI) - Calit2


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Panel studies power in SoCs

Ron Wilson
EE Times
(11/04/2005 6:35 PM EST)

NEWPORT BEACH, Calif. — A panel discussion at the 3rd International System-on-Chip Conference here this week attempted to skip past the academic science projects and the rosy vendor marketing and explore what was really feasible today in the challenging area of power management.

The first question the panel attacked was the need for more power management in the first place. Couldn't today's designs get by with standby, sleep, doze and coma modes, like their 180-nm predecessors?

"One sleep mode is not enough any more,” declared David Flynn, engineering fellow at ARM Ltd. "The power demands of applications now require far too many techniques."

On the issue of what to do about the problem, the panel was more divided. Steve Liebson, technology evangelist at Tensilica Inc., for his part, argued that the place to start was with architectural change.

"Begin by unlearning bad habits," he advised. "There is a huge amount of parallelism available in many applications — instruction-level parallelism in inner loops, data parallelism that can be exploited with SIMD instructions. Stop thinking about a single CPU fast enough for your peak load, and take advantage of the parallelism. That allows you to lower the clock, and the voltage, and that is the biggest thing you can do to reduce both active and leakage power."

Susan Runowicz-Smith, marketing manager for the Silicon Design Chain Initiative at Cadence Design Systems Inc., agreed. She described significant power savings that could be achieved nearly independent of architectural decisions by aggressive use of clock gating, power gating, voltage islands and libraries with a range of threshold voltages.

But many of these techniques have been limited to large, well-funded design teams in the past, she said, because they were all essentially manual.

"We are working to automate these techniques,” she said. “For instance, today we can accept a design with multiple static voltage domains, automatically insert level shifters where necessary, and move through physical design and timing closure with a single production tool flow."

This ongoing project has taken close collaboration between Cadence, Applied Materials, ARM and TSMC, she said. And it still has far to go before all the currently known techniques — such as power gating without losing state, dynamic voltage/frequency scaling and dynamic threshold control — can be implemented automatically.

ARM's Flynn agreed that we needed more help from the tools. "Today, everything requires huge amounts of analysis," he said.

"For example, if I want to dynamically change voltages, I suddenly need libraries that are characterized at a large number of operating points — or, better, accurate current models rather than voltage models,” he said. “We need more help from the tools. And ultimately, we need a new way to describe designs. Verilog is not the right medium for all the things a designer has to tell the tool chain about his design."







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