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The 14th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

 October 19 & 20, 2016

University of California, Irvine (UCI) - Calit2

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Dr. Ramon Acosta, Vice President of Engineering for Nascentric to Present at International System on Chip Conference and Exhibit

 

Oct 26, 2005 (BUSINESS WIRE) -- Dr. Ramon Acosta, Vice President of Engineering for Nascentric, Inc. will deliver a presentation discussing state-of-the-art analysis solutions addressing nanometer design issues related to timing, power and signal integrity at the International SoC Conference. These solutions enable designers to quickly analyze larger and more complex circuits, improve design quality and facilitate higher yields.

 

Dr. Acosta will discuss Nascim, a new generation of Fast-SPICE simulation. Nascim is the first in a series of advanced simulation and analysis products being developed by Nascentric. Initially focused on digital logic and memories, Nascim provides 2X-10X the performance of other Fast-SPICE simulators and exceeds the accuracy and capacity requirements set for leading-edge process technologies.

 

"As complex SoC and ASIC designs move toward 65nm and 45nm technologies, nanometer design-related issues such as timing, power, signal integrity become more and more problematic, and the need for Nascentric's innovative and leading edge EDA solutions becomes even more evident," said Farhad Mafie, president and CEO of the Savant Company Inc. and SoC Conference organizer. "We are very delighted to have Nascentric's participation and technology demonstration in this targeted and informative SoC Conference and Exhibit."

 

For more information call 512-225-8800, or visit us on the web at www.nascentric.com.

 

3RD INTERNATIONAL SYSTEM-ON-CHIP (SoC) CONFERENCE & EXHIBIT Date: November 2, 2005,  Time: 1:30 pm - 4:30 pm,  Location: Radisson Hotel, 4545 MacArthur Boulevard, Newport Beach, California 92660, USA

 

About Nascentric

Nascentric is a privately held company headquartered in Austin, Texas. Nascentric delivers state-of-the-art analysis solutions addressing nanometer design issues related to timing, power and signal integrity that enable designers to quickly analyze larger and more complex circuits, improve design quality and facilitate higher yields. The Nascentric management team brings decades of combined electrical engineering and electronic design automation experience to bear on the challenge of delivering full-chip simulation and analysis focused on eliminating silicon re-spins due to nanometer effects.

 

Nascentric, the Nascentric logo and Nascim are registered trademarks of Nascentric, Inc. All other company or product names are the registered trademarks or trademarks of their respective owners.

 

 

 

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