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By Steve Leibson

May 13, 2004



90 nm checklist: Avoid these gotchas in your SOC design

Panelists at the 1st International SOC Design Conference produced an excellent checklist of items to watch out for when designing SOCs using 90nm technology.

  • Design complexity. With millions, tens of millions, or hundreds of millions of transistors available on a 90nm SOC, the sheer complexity of the design threatens the success of the project because of EDA tool limitations. The current crop of EDA tools was not developed to handle chip designs this large.

  • Designer productivity. Moore’s Law increases the number of transistors available on an SOC by roughly 58% per year while designer productivity, spurred by design-tool improvements, has increased at only about 21% per year. These numbers have held constant for the past two decades. The sheer number of transistors now available on a chip far outstrips the design team’s ability to harness them efficiently. Consequently, chip-design teams are unable to exploit the full benefit of 90nm silicon process technology because they may leave a lot of transistors on the table.

  • Manufacturability (design-specific failures). Chip complexity has risen to the point that it may no longer be possible to design manufacturable devices because each fabricated chip is likely to have at least one operational flaw. While semiconductor memory and FPGA designers have successfully dealt with this phenomenon for years (by adding redundant circuits), SOC designers have never faced this problem. Until now.

  • Diagnostics. Allied with the problems of device and design complexity, SOCs built with 90nm technology may require far too much time under the probe head of an IC tester to economically verify proper operation and to diagnose problems. Far more reliance on parallel BIST-based testing will be needed.

  • Power dissipation. At 90nm, SOCs will dissipate about as much power through static-power leakage as they will through dynamic-power switching. Virtual Silicon’s Ford said, "Power is the crisis at 90nm." While dynamic power dissipation can be reduced through aggressive fine-grained clock gating, EDA tools and design techniques that reduce static power dissipation through leakage have yet to be widely adopted because they are not yet automated. "Things will change [in June] at DAC." said Magma’s Jones.

  • Process variability. IC designers have always had to deal with "lot-to-lot" and even "wafer-to-wafer" process variability. At 90nm, add "across-the-die" variability to the list of process-variation dimensions. As a result, a working chip design doesn’t necessarily produce a 90nm SOC that yields economically. Coping with such variability may require a more adaptive approach to SOC design.

  • Adapting to the consumer-electronics marketing model. Volume production of electronic equipment is now dominated by consumer electronics devices. Unlike network servers, the first production run of 50 consumer electronics boxes can’t have an introductory unit price of $10k followed by gradual price reductions. Consumer electronics products must hit the market priced at no more than a few hundred dollars. In addition, consumers have rapidly expanding expectations with respect to performance improvements, new features and functions, and product reliability. Many consumer electronics products need 10-year life spans.

  • First-time design success is mandatory. Competitive pressures, global competition, and just-in-time corporate funding can quickly bury a company that stumbles on the way to market. If a 90nm chip design must be respun, either the delay in product introduction, the loss of first-to-market profits, or the added expense of a design spin can kill off a design team, a division, or an entire company.

  • Wire-level modeling is now critical to timing analysis. Actually, this issue surfaced at the 130nm process node. Wires are now much slower than gates. Wire delay is an even bigger problem at 90nm. Some companies such as IBM are talking about switching from Monte Carlo optimizations based on static timing analyses to statistical timing analysis to deal with this issue and to deal with 90nm process variations.

  • Many EDA tools for chip design are breaking because the 90nm device models are almost universally wrong. "They’re based on inaccurate Spice models." said Virtual Silicon’s Ford. More accurate models are available. Virtual Silicon relies on revamped and revised 90nm device models from Jones’ division at Magma.

  • On-chip supply voltages used to be fixed. Now they’re variable. Current EDA tools are brain-dead with respect to IC designs that employ variable power-supply voltages.

  • Similarly, 90nm chip designs increasingly employ voltage islands so that different blocks can operate at different voltages (and clock rates). There’s no EDA tool automation to support this sort of design, at least not yet.

  • Chip-design teams have lost the ability to consider new design tools and flows and are unable to switch to the best available design tools after more than a decade of ASIC and SOC design based on a remarkably stable design methodology and tool flow. Now that the 90nm process node is creating some major rifts in these existing techniques, the stability of the last decade is becoming a problem. Engineering inertia and lethargy are always problems no matter where you find them.

  • Death by verification/verification is forever. Verifying the design of 90nm chips with tens of millions of gates using EDA tools and techniques that were initially developed when chips only had a few hundred thousand gates is a one-way ticket to design limbo. The industry has never mastered SOC block reuse (which can eliminate the need for a lot of verification). The endemic lack of a formal reuse regimen is fatal at 90nm.

  • Platform-based chip design, intended to make 90nm SOC technology more accessible to a wider number of design teams, makes SOC architectures look like warmed-over single-board computers from the 1980s. Virtual Silicon’s Ford quipped, "Platforms always look like [clothes sold by] The Gap. They appeal to many, but they don’t fit anyone well."

  • Block partitioning of 90nm SOCs is based on design habits developed when EDA tools had much less capacity and sophistication than they do today. Design methodology is therefore artificially restricted to blocks that are smaller and simpler than necessary and chip architecture is consequently limited in scope.

  • The design cost for a full-up, cell-based SOC is $30-50 million (with 10% of this budget earmarked for EDA tools). Although chips based on ASIC design flows (vendor-managed back-end IC design) may only cost 1/3 of this sum, the resulting chips based on ASIC flows are slower, bigger, and more expensive than COT designs. Consequently, 90nm SOC design is a big-player game for now.

Yet for all these problems, 90nm SOC design is occurring and is even successful, so some design teams are overcoming (or simply ignoring) many of these problems. The representatives on the panel that work for EDA tools vendors licked their lips in anticipation of the long lines of buyers for their new and improved design tools—the price of admission to the 90nm design game. "How much will these new tools cost?" asked one conference participant. "How much have you got?" deadpanned Cadence’s Carlson with a Cheshire-cat grin. I’m almost sure he was joking.

Steve Leibson was formerly the VP of Content for MDR.







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