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The 14th International System-on-Chip (SoC)

Conference, Exhibit & Workshops

 October 19 & 20, 2016

University of California, Irvine (UCI) - Calit2

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September 2006





Expert Viewpoint,  VSIA Org

System-on-Chip and On-Chip Communication Challenges

From uniprocessor SISD (Single Instruction stream, Single Data stream) systems to multiprocessing architectures using either SIMD (Single Instruction stream, Multiple Data streams), MIMD (Multiple Instruction streams, Multiple Data streams), etc. approaches, one of the most important topics in the computer architecture field has always been the communication network (the bus architecture) among processor(s), cache(s), memory(ies), and I/O controller(s) sub-system(s). Many multiprocessor interconnections architecture such as Multilevel Switched-Network Systems, Hypercubes, Shuffle-Exchange Interconnection, and Crossbar-connected systems have been implemented in various supercomputers, all with their own pros and cons and related challenges.

To bring to fruition the exceptional computational power of many available processing units (including DSPs), the communication network ľamong various system blocks ľnot only must provide very high performance as far as latency and bandwidth, but it must also be able to resolve bus contentions under extremely heavy loads, provide fairness, and hide as much as possible its own physical and system-related overheads.

As we are moving from 90 nm to 65 nm and now 45 nm technologies, we are able to interconnect tens of synergistic processing units, a control processor, distributed cache sub-system, various blocks and types of memories, and many I/O controllers all in one device. And obviously the same types of communication network issues and challenges that we have in complex MIMD systems are now reappearing in these multiprocessing (multi-cores) based systems that are being designed using System-on-Chip methodologies and techniques.

As multi-core paradigm on a single chip become ubiquitous, integrating tens of processor cores (with the current technologies) and in the near future, as 65nm and 45nm becomes affordable, integrating hundreds of cores into complex ASSPs for applications such as advanced embedded systems, gaming consoles, and supercomputers, will become the trend in the next generation devices. And the need for a high-performance, low latency, low-overhead communication network sub-system becomes even more obvious.

Today there are several companies whose sole product (and solution) is targeted to offer high-performance communication network sub-system solutions for complex multi-core based new designs. How these solutions get integrated with various cores and IPs (from many vendors) and how effectively they can develop third party support (including support from VSIA and the EDA community) will play an important role in how well they would be able to gain acceptance (and eventually design wins) in the chip design communities around the world.

In the Savant 4th International System-on-Chip (SoC) Conference and Exhibit on November 1 and 2, 2006, we have dedicated an entire track (i.e., Network-on-Chip Architectures for Complex SoCs) to this challenging topic with presentations from industry (STMicro and Sonics) as well as academic research centers (UCI and Pacific Northwest National Laboratory). This will be followed by a panel discussion moderated by Ron Wilson (EDN magazine), addressing Architectural and Performance-Related Challenges for Complex SoCs with emphasize on Network-on-Chip (NoC.)






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